LPC47M102S-MC View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
LPC47M102S-MC
SMSC -> Microchip
'LPC47M102S-MC' PDF : 188 Pages View PDF
BIT 3 DMAEN
PC/AT and Model 30 Mode:
Writing this bit to logic "1" will enable the DMA and interrupt functions. This bit being a logic "0" will disable the DMA and
interrupt functions. This bit is a logic "0" after a reset and in these modes.
PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset, this bit will be cleared to a
logic "0".
BIT 4 MOTOR ENABLE 0
This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active.
DRIVE
0
1
DOR VALUE
1CH
2DH
BIT 5 MOTOR ENABLE 1
This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active.
BIT 6 MOTOR ENABLE 2
The MTR2 disk interface output is not supported in the LPC47M10x.
BIT 7 MOTOR ENABLE 3
The MTR3 disk interface output is not supported in the LPC47M10x.
TAPE DRIVE REGISTER (TDR)
Address 3F3 READ/WRITE
The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support
to a particular drive during initialization. Any future references to that drive automatically invokes tape support. The TDR
Tape Select bits TDR.[1:0] determine the tape drive number. Table 3 illustrates the Tape Select Bit encoding. Note that
drive 0 is the boot device and cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are
tristated when read. The TDR is unaffected by a software reset.
Table 3 - Tape Select Bits
TAPE SEL1 TAPE SEL0
DRIVE
(TDR.1)
(TDR.0)
SELECTED
0
0
None
0
1
1
1
0
2
1
1
3
Table 4 - Internal 2 Drive Decode - Normal
DRIVE SELECT OUTPUTS
DIGITAL OUTPUT REGISTER
(ACTIVE LOW)
Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0
nDS1
nDS0
X
X
X
1
0
0
1
0
X
X
1
X
0
1
0
1
X
1
X
X
1
0
1
1
1
X
X
X
1
1
1
1
0
0
0
0
X
X
1
1
MOTOR ON OUTPUTS
(ACTIVE LOW)
nMTR1
nMTR0
nBIT 5
nBIT 4
nBIT 5
nBIT 4
nBIT 5
nBIT 4
nBIT 5
nBIT 4
nBIT 5
nBIT 4
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