LPC47M102S-MC View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
LPC47M102S-MC
SMSC -> Microchip
'LPC47M102S-MC' PDF : 188 Pages View PDF
BIT 2 through 4 PRECOMPENSATION SELECT
These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 7
shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track
number to start precompensation. this starting track number can be changed by the configure command.
BIT 5 UNDEFINED
Should be written as a logic "0".
BIT 6 LOW POWER
A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and
data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset
or access to the Data Register or Main Status Register.
BIT 7 SOFTWARE RESET
This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing.
Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located at the offset 0x1F in the runtime
register block. Separator circuits will be turned off. The controller will come out of manual low power.
PRECOMP
432
111
001
010
011
100
101
110
000
Table 7 - Precompensation Delays
PRECOMPENSATION DELAY (nsec)
<2Mbps
2Mbps
0.00
0
41.67
20.8
83.34
41.7
125.00
62.5
166.67
83.3
208.33
104.2
250.00
125
Default
Default
Default: See Table 10
DRIVE RATE
Table 8 - Data Rates
DATA RATE
DATA RATE
DRT1 DRT0 SEL1 SEL0 MFM FM
0
0
1
1
1Meg
---
0
0
0
0
500
250
0
0
0
1
300
150
0
0
1
0
250
125
0
1
1
1
1Meg
---
0
1
0
0
500
250
0
1
0
1
500
250
0
1
1
0
250
125
1
0
1
1
1Meg
---
1
0
0
0
500
250
1
0
0
1
2Meg
---
1
0
1
0
250
125
DENSEL
1
1
0
0
1
1
0
0
1
1
0
0
DRATE(1)
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format
01 = 3-Mode Drive
10 = 2 Meg Tape
Note 1: The DRATE and DENSEL values are mapped onto the DRVDEN pins.
Page 27
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