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LPC47M112-MC View Datasheet(PDF) - SMSC -> Microchip

Part Name
Description
MFG CO.
'LPC47M112-MC' PDF : 204 Pages View PDF
Enhanced Super I/O Controller with LPC Interface
Datasheet
20 TIMING DIAGRAMS FOR SER_IRQ CYCLE
A) Start Frame timing with source sampled a low pulse on IRQ1
PCI_CLK
SER_IRQ
SL START FRAME
IRQ0 FRAME IRQ1 FRAME IRQ2 FRAME
or
H
H
RT SRT SRT SRT
START1
Drive Source IRQ1 Host Controller
None
IRQ1
None
Note: H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample
Note 1: Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge
hierarchy in a synchronous bridge design.
B) Stop Frame Timing with Host using 17 SER_IRQ sampling period.
IRQ14
FRAME
SRT
PCI_CLK
SER_IRQ
Driver
None
IRQ15
FRAME
S RT
IRQ15
IOCHCK#
FRAME
SRT
None
STOP FRAME
I2
H
RT
STOP 1
Host Controller
NEXT CYCLE
START 3
Note: H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle
Note 1: The next SER_IRQ cycle’s Start Frame pulse may or may not start immediately after the turn-
around clock of the Stop Frame.
Note 2: There may be none, one or more Idle states during the Stop Frame.
Note 3: Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
SMSC DS – LPC47M112
Page 102
DATASHEET
Rev. 02-16-07
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