LPC47M112-MC View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

LPC47M112-MC

Enhanced Super I/O Controller with LPC Interface / Dual Game Port Interface

SMSC -> Microchip 

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Enhanced Super I/O Controller with LPC Interface

Datasheet

9 FLOPPY DISK CONTROLLER

The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives.

The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and

Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC

XT/AT compatibility in addition to providing data overflow and underflow protection.

The FDC is compatible to the 82077AA using

SMSC's proprietary floppy disk controller core.

9.1 FDC Internal Registers

The Floppy Disk Controller contains eight internal registers which facilitate the interfacing between the host

microprocessor and the disk drive. Table 2 shows the addresses required to access these registers. Registers other

than the ones shown are not supported. The rest of the description assumes that the primary addresses have been

selected.

PRIMARY

ADDRESS

3F0

3F1

3F2

3F3

3F4

3F4

3F5

3F6

3F7

3F7

Table 2 - Status, Data and Control Registers

(Shown with base addresses of 3F0 and 370)

SECONDARY

ADDRESS

370

371

372

373

374

374

375

376

377

377

R/W

REGISTER

R

Status Register A (SRA)

R

Status Register B (SRB)

R/W Digital Output Register (DOR)

R/W Tape Drive Register (TSR)

R

Main Status Register (MSR)

W Data Rate Select Register (DSR)

R/W Data (FIFO)

Reserved

R

Digital Input Register (DIR)

W Configuration Control Register (CCR)

STATUS REGISTER A (SRA)

Address 3F0 READ ONLY

This register is read-only and monitors the state of the internal interrupt signal and several disk interface pins in PS/2

and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins

D0 - D7 are held in a high impedance state for a read of address 3F0.

PS/2 Mode

7

6

5

4

3

2

1

0

INT

nDRV2 STEP nTRK0 HDSEL nINDX nWP DIR

PENDING

RESET

0

1

0

N/A

0

N/A N/A

0

COND.

BIT 0 DIRECTION

Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic "0" indicates

outward direction.

BIT 1 nWRITE PROTECT

Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is write protected.

SMSC DS – LPC47M112

Page 25

DATASHEET

Rev. 02-16-07

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