LPC47M112-MC View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
LPC47M112-MC
SMSC -> Microchip
'LPC47M112-MC' PDF : 204 Pages View PDF
Enhanced Super I/O Controller with LPC Interface
Datasheet
PS/2 Model 30 Mode
7
6
nDRV2 nDS1
RESET N/A
1
COND.
5
nDS0
1
4
WDATA
F/F
0
3
RDATA
F/F
0
2
WGATE
F/F
0
1
nDS3
1
0
nDS2
1
BIT 0 nDRIVE SELECT 2
The DS2 disk interface is not supported.
BIT 1 nDRIVE SELECT 3
The DS3 disk interface is not supported.
BIT 2 WRITE GATE
Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is
cleared by the read of the DIR register.
BIT 3 READ DATA
Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is
cleared by the read of the DIR register.
BIT 4 WRITE DATA
Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is
cleared by the read of the DIR register. This bit is not gated with WGATE.
BIT 5 nDRIVE SELECT 0
Active low status of the DS0 disk interface output.
BIT 6 nDRIVE SELECT 1
Active low status of the DS1 disk interface output.
BIT 7 nDRV2
Active low status of the DRV2 disk interface input. Note: This function is not supported.
DIGITAL OUTPUT REGISTER (DOR)
Address 3F2 READ/WRITE
The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for
the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be
written to at any time.
RESET
COND.
7
MOT
EN3
0
6
MOT
EN2
0
5
MOT
EN1
0
4
MOT
EN0
0
3
DMAEN
0
2
nRESET
0
1
DRIVE
SEL1
0
0
DRIVE
SEL0
0
BIT 0 and 1 DRIVE SELECT
These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time.
BIT 2 nRESET
A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1" is written to
this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR
register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register
is a valid method of issuing a software reset.
SMSC DS – LPC47M112
Page 28
DATASHEET
Rev. 02-16-07
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