LPC47M112-MC View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

LPC47M112-MC

Enhanced Super I/O Controller with LPC Interface / Dual Game Port Interface

SMSC -> Microchip 

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Enhanced Super I/O Controller with LPC Interface

Datasheet

3. The chip places address or data on PData bus, clears PDIR, and asserts nWRITE.

4. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE

signal is valid.

5. Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the chip may begin the

termination phase of the cycle.

6. a) The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the termination phase. If it has

not already done so, the peripheral should latch the information byte now.

b) The chip latches the data from the internal data bus for the PData bus and drives the sync that indicates that no

more wait states are required followed by the TAR to complete the write cycle.

7. Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and

acknowledging the termination of the cycle.

8. Chip may modify nWRITE and nPDATA in preparation for the next cycle.

SMSC DS – LPC47M112

Page 86

DATASHEET

Rev. 02-16-07

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