LPC47M14F-NC View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
LPC47M14F-NC
SMSC -> Microchip
'LPC47M14F-NC' PDF : 205 Pages View PDF
Table 32 – Reset Function Table
REGISTER/SIGNAL
Interrupt Enable Register
Interrupt Identification Reg.
FIFO Control
Line Control Reg.
MODEM Control Reg.
Line Status Reg.
MODEM Status Reg.
TXD1, TXD2
INTRPT (RCVR errs)
INTRPT (RCVR Data Ready)
INTRPT (THRE)
OUT2B
RTSB
DTRB
OUT1B
RCVR FIFO
XMIT FIFO
RESET CONTROL
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET/Read LSR
RESET/Read RBR
RESET/ReadIIR/Write THR
RESET
RESET
RESET
RESET
RESET/
FCR1*FCR0/_FCR0
RESET/
FCR1*FCR0/_FCR0
RESET STATE
All bits low
Bit 0 is high; Bits 1 - 7 low
All bits low
All bits low
All bits low
All bits low except 5, 6 high
Bits 0 - 3 low; Bits 4 - 7 input
High
Low
Low
Low
High
High
High
High
All Bits Low
All Bits Low
Table 33 – Register Summary for an Individual UART Channel
REGISTER
ADDRESS*
ADDR = 0
DLAB = 0
ADDR = 0
DLAB = 0
ADDR = 1
DLAB = 0
ADDR = 2
ADDR = 2
ADDR = 3
REGISTER NAME
REGISTER
SYMBOL
BIT 0
BIT 1
Receive Buffer Register (Read Only)
RBR
Data Bit 0 Data Bit 1
(Note 1)
Transmitter Holding Register (Write
Only)
THR
Data Bit 0 Data Bit 1
Interrupt Enable Register
IER Enable
Enable
Received Transmitter
Data
Holding
Available Register
Interrupt
Empty
(ERDAI)
Interrupt
(ETHREI)
Interrupt Ident. Register (Read Only)
IIR
"0" if
Interrupt ID
Interrupt
Bit
Pending
FIFO Control Register (Write Only)
FCR FIFO Enable RCVR FIFO
(Note 7)
Reset
Line Control Register
LCR Word
Word
Length
Length
Select Bit 0 Select Bit 1
(WLS0)
(WLS1)
ADDR = 4
MODEM Control Register
ADDR = 5
Line Status Register
MCR
LSR
Data
Terminal
Ready
(DTR)
Request to
Send (RTS)
Data Ready Overrun
(DR)
Error (OE)
SMSC DS – LPC47M14X
Page 69
Rev. 03/19/2001
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