LPC47M14F-NC View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

LPC47M14F-NC

128 Pin Enhanced Super I/O Controller with an LPC Interface and USB Hub

SMSC -> Microchip 

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REGISTER

ADDRESS*

ADDR = 6

REGISTER NAME

MODEM Status Register

ADDR = 7

ADDR = 0

DLAB = 1

ADDR = 1

DLAB = 1

Scratch Register (Note 4)

Divisor Latch (LS)

Divisor Latch (MS)

REGISTER

SYMBOL

BIT 0

MSR

Delta Clear

to Send

(DCTS)

SCR Bit 0

DDL Bit 0

BIT 1

Delta Data

Set Ready

(DDSR)

Bit 1

Bit 1

DLM Bit 8

Bit 9

*DLAB is Bit 7 of the Line Control Register (ADDR = 3).

Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.

Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.

Table 33 – Register Summary for an Individual UART Channel (continued)

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

Data Bit 2

Data Bit 3

Data Bit 4

Data Bit 5

Data Bit 6

Data Bit 7

Data Bit 2

Data Bit 3

Data Bit 4

Data Bit 5

Data Bit 6

Data Bit 7

Enable

Enable

0

0

0

0

Receiver Line MODEM

Status

Status

Interrupt

Interrupt

(ELSI)

(EMSI)

Interrupt ID Bit Interrupt ID Bit 0

0

FIFOs

FIFOs

(Note 5)

Enabled

Enabled

(Note 5)

(Note 5)

XMIT

Reset

FIFO DMA Mode Reserved

Select (Note

6)

Reserved

RCVR Trigger RCVR Trigger

LSB

MSB

Number of Parity Enable Even Parity Stick Parity

Stop

Bits (PEN)

Select (EPS)

(STB)

Set Break

Divisor Latch

Access Bit

(DLAB)

OUT1

OUT2

Loop

0

0

0

(Note 3)

(Note 3)

Parity

(PE)

Error Framing Error Break

(FE)

Interrupt (BI)

Transmitter

Holding

Register

(THRE)

Transmitter Error in RCVR

Empty (TEMT) FIFO (Note 5)

(Note 2)

Trailing Edge Delta Data Clear to Send Data

Set Ring Indicator Data Carrier

Ring Indicator Carrier Detect (CTS)

Ready (DSR) (RI)

Detect (DCD)

(TERI)

(DDCD)

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 10

Bit 11

Bit 12

Bit 13

Bit 14

Bit 15

Note 3: This bit no longer has a pin associated with it.

Note 4: When operating in the XT mode, this register is not available.

Note 5: These bits are always zero in the non-FIFO mode.

Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip.

Note 7: The UART1 and UART2 FCR’s are shadowed in the UART1 FIFO Control Shadow Register (runtime

register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at offset 0x21).

SMSC DS – LPC47M14X

Page 70

Rev. 03/19/2001

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