LPC47M14X View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
'LPC47M14X' PDF : 205 Pages View PDF
6.13.9 Latches On Keyboard and Mouse IRQs
The implementation of the latches on the keyboard and mouse interrupts is shown below.
KLATCH Bit
8042
KINT
VCC
DQ
CLR
KINnTew
RD 60
FIGURE 6 – KEYBOARD LATCH
MLATCH Bit
8042
MINT
VCC
DQ
CLR
RD 60
MINnTew
FIGURE 7 – MOUSE LATCH
The KLATCH and MLATCH bits are located in the KRST_GA20 register, in Logical Device 7 at 0xF0.
These bits are defined as follows:
Bit[4]: MLATCH – Mouse Interrupt latch control bit. 0=MINT is the 8042 MINT ANDed with Latched MINT
(default), 1=MINT is the latched 8042 MINT.
Bit[3]: KLATCH – Keyboard Interrupt latch control bit. 0=KINT is the 8042 KINT ANDed with Latched
KINT (default), 1=KINT is the latched 8042 KINT.
See the “Configuration” section for a description of this register.
SMSC DS – LPC47M14X
Page 108
Rev. 03/19/2001
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