6.14 GENERAL PURPOSE I/O
The LPC47M14x provides a set of flexible Input/Output control functions to the system designer through the 37
dedicated independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform basic I/O and
many of them can be individually enabled to generate an SMI and a PME.
6.14.1 GPIO Pins
The following pins include GPIO functionality. These pins are defined in the table below. All GPIOs default to the
GPIO function except for GP34 and GP35 which default to IRRX2 and IRTX2.
PIN
NAME
1
GP40 /DRVDEN0
2
GP41 /DRVDEN1 /EETI
17 GP42 /nIO_PME
28 GP43/DDRC/EETI
32 GP10 /J1B1
33 GP11 /J1B2
34 GP12 /J2B1
35 GP13 /J2B2
36 GP14 /J1X
37 GP15 /J1Y
38 GP16 /J2X
39 GP17 /J2Y
41 GP20 /P17
42 GP21 /P16 /EETI
43 GP22 /P12 /EETI
45 GP24 (SYSOPT)
46 GP25 /MIDI_IN
47 GP26 /MIDI_OUT
48 GP60 /LED1 /EETI
49 GP61 /LED2 /EETI
50 GP27/nIO_SMI
51 GP30 /FAN_TACH2
52 GP31 /FAN_TACH1
54 GP32 /FAN2
55 GP33 /FAN1
61 IRRX2/GP34
62 IRTX2/GP35
63 GP36 /nKBDRST
64 GP37 /A20M
92 GP50 /nRI2
94 GP51 /nDCD2
95 GP52 /RXD2
96 GP53 /TXD2
97 GP54 /nDSR2
98 GP55 /nRTS2
99 GP56 /nCTS2
100 GP57 /nDTR2
SMSC DS – LPC47M14X
Page 110
Rev. 03/19/2001