LPC47M192 View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
'LPC47M192' PDF : 228 Pages View PDF
6 POWER FUNCTIONALITY
The LPC47M192 has four power planes: VCC, HVCC, VREF, and VTR.
6.1 VCC/HVCC Power
The LPC47M192 is a 3.3 Volt part. The VCC/HVCC supply is 3.3 Volts (nominal). VCC is supply for Super I/O
Block, and HVCC is supply for the Hardware Monitoring Block. See the “Operational Description” Section and
the “Maximum Current Values” subsection.
6.1.1 3 VOLT OPERATION / 5 VOLT TOLERANCE
The LPC47M192 is a 3.3-Volt part. It is intended solely for 3.3V applications. Non-LPC bus pins are 5V
tolerant; that is, the operating input voltage is 5.5V Max, and the I/O buffer output pads are backdrive
protected (they do not impose a load on any external VCC/HVCC powered circuitry). The 5V tolerant pins are
applicable to the Super I/O Block only.
The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling. These pins are:
LAD[3:0]
LFRAME#
LDRQ#
LPCPD#
The input voltage for all other pins is 5.5V max. These pins include all non-LPC Bus pins and the following pins in the
Super I/O Block:
PCI_RESET#
PCI_CLK
SER_IRQ
IO_PME#
The Hardware Monitoring Block digital pins are 3.3V only.
6.2 VREF Pin
The LPC47M192 has a reference voltage pin input on pin 44 of the part. This reference voltage can be
connected to either a 5V supply or a 3.3V supply. It is used for the game port. See the “GAME PORT
LOGIC” section.
6.3 VTR Support
The LPC47M192 requires a trickle supply (VTR) to provide sleep current for the programmable wake-up events
in the PME interface when VCC is removed. The VTR supply is 3.3 Volts (nominal). See the Operational
Description Section. The maximum VTR current that is required depends on the functions that are used in the
part. See Trickle Power Functionality subsection and Maximum Current Values subsection. If the
LPC47M192 is not intended to provide wake-up capabilities on standby current, VTR can be connected to VCC.
VTR powers the IR interface, the PME configuration registers, and the PME interface. The VTR pin generates a
VTR Power-on-Reset signal to initialize these components.
Note: If VTR is to be used for programmable wake-up events when VCC is removed, VTR must be at its full
minimum potential at least 10 µs before Vcc begins a power-on cycle. When VTR and Vcc are fully powered, the
potential difference between the two supplies must not exceed 500mV.
6.3.1 TRICKLE POWER FUNCTIONALITY
When the LPC47M192 is running under VTR only (VCC removed), PME wakeup events are active and (if
enabled) able to assert the nIO_PME pin active low. The following lists the wakeup events:
UART 1 Ring Indicator
UART 2 Ring Indicator
Keyboard data
Mouse data
“Wake on Specific Key” Logic
SMSC DS – LPC47M192
Page 23
Rev. 03/30/05
DATASHEET
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