LPC47M192 View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
'LPC47M192' PDF : 228 Pages View PDF
7.3 LPC Interface
The following sub-sections specify the implementation of the LPC bus.
7.3.1 LPC INTERFACE SIGNAL DEFINITION
The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI
33MHz electrical signal characteristics.
SIGNAL
NAME
LAD[3:0]
LFRAME#
PCI_RESET#
LDRQ#
nIO_PME
TYPE
I/O
Input
Input
Output
OD
LPCPD#
Input
SER_IRQ
PCI_CLK
I/O
Input
DESCRIPTION
LPC address/data bus. Multiplexed command, address and data bus.
Frame signal. Indicates start of new cycle and termination of broken cycle
PCI Reset. Used as LPC Interface Reset.
Encoded DMA/Bus Master request for the LPC interface.
Power Mgt Event signal. Allows the LPC47M192 to request wakeup.
Powerdown Signal. Indicates that the LPC47M192 should prepare for power to be shut
on the LPC interface.
Serial IRQ.
PCI Clock.
Note: The CLKRUN# signal is not implemented in this part.
7.3.2 LPC CYCLES
The following cycle types are supported by the LPC protocol.
I/O Write
I/O Read
DMA Write
DMA Read
CYCLE TYPE
1 Byte
1 Byte
1 Byte
1 Byte
TRANSFER SIZE
LPC47M192 ignores cycles that it does not support.
7.3.3 FIELD DEFINITIONS
The data transfers are based on specific fields that are used in various combinations, depending on the cycle
type. These fields are driven onto the LAD[3:0] signal lines to communicate address, control and data
information over the LPC bus between the host and the LPC47M192. See the Low Pin Count (LPC) Interface
Specification Revision 1.0 from Intel, Section 4.2 for definition of these fields.
7.3.4 LFRAME# USAGE
LFRAME# is used by the host to indicate the start of cycles and the termination of cycles due to an abort or
time-out condition. This signal is to be used by the LPC47M192 to know when to monitor the bus for a cycle.
This signal is used as a general notification that the LAD[3:0] lines contain information relative to the start or
stop of a cycle, and that the LPC47M192 monitors the bus to determine whether the cycle is intended for it.
The use of LFRAME# allows the LPC47M192 to enter a lower power state internally. There is no need for the
LPC47M192 to monitor the bus when it is inactive, so it can decouple its state machines from the bus, and
internally gate its clocks.
When the LPC47M192 samples LFRAME# active, it immediately stops driving the LAD[3:0] signal lines on the
next clock and monitor the bus for new cycle information.
The LFRAME# signal functions as described in the Low Pin Count (LPC) Interface Specification, Revision 1.0.
SMSC DS – LPC47M192
Page 28
DATASHEET
Rev. 03/30/05
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