LPC47M192 View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
'LPC47M192' PDF : 228 Pages View PDF
Note:
The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located at the offset 0x1F in the
runtime register block Separator circuits will be turned off. The controller will come out of manual low
power.
DRIVE RATE
DRT1 DRT0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
Table 8 – Data Rates
DATA RATE
SEL1 SEL0
DATA RATE
MFM FM
DENSEL
1
1
1Meg
---
1
0
0
500
250
1
0
1
300
150
0
1
0
250
125
0
1
1
1Meg
---
1
0
0
500
250
1
0
1
500
250
0
1
0
250
125
0
1
1
1Meg
---
1
0
0
500
250
1
0
1
2Meg
---
0
1
0
250
125
0
DRATE(1)
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format
01 = 3-Mode Drive
10 = 2 Meg Tape
Note 1: The DRATE and DENSEL values are mapped onto the DRVDEN pins.
DT1 DT0
0
0
1
0
0
1
1
1
Table 9 – DRVDEN Mapping
DRVDEN1 (1)
DRATE0
DRATE0
DRATE0
DRATE1
DRVDEN0 (1)
DENSEL
DRATE1
nDENSEL
DRATE0
DRIVE TYPE
4/2/1 MB 3.5”
2/1 MB 5.25” FDDS
2/1.6/1 MB 3.5” (3-MODE)
PS/2
Table 10 – Default Precompensation Delays
DATA RATE
2 Mbps
1 Mbps
500 Kbps
300 Kbps
250 Kbps
PRECOMPENSATION
DELAYS
20.8 ns
41.67 ns
125 ns
125 ns
125 ns
SMSC DS – LPC47M192
Page 37
DATASHEET
Rev. 03/30/05
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