Table 11 – FIFO Service Delay
FIFO THRESHOLD
EXAMPLES
1 byte
2 bytes
8 bytes
15 bytes
MAXIMUM DELAY TO SERVICING AT
2 Mbps DATA RATE
1 x 4 us - 1.5 us = 2.5 us
2 x 4 us - 1.5 us = 6.5 us
8 x 4 us - 1.5 us = 30.5 us
15 x 4 us - 1.5 us = 58.5 us
FIFO THRESHOLD
EXAMPLES
1 byte
2 bytes
8 bytes
15 bytes
MAXIMUM DELAY TO SERVICING AT
1 Mbps DATA RATE
1 x 8 us - 1.5 us = 6.5 us
2 x 8 us - 1.5 us = 14.5 us
8 x 8 us - 1.5 us = 62.5 us
15 x 8 us - 1.5 us = 118.5 us
FIFO THRESHOLD
EXAMPLES
1 byte
2 bytes
8 bytes
15 bytes
MAXIMUM DELAY TO SERVICING AT
500 Kbps DATA RATE
1 x 16 us - 1.5 us = 14.5 us
2 x 16 us - 1.5 us = 30.5 us
8 x 16 us - 1.5 us = 126.5 us
15 x 16 us - 1.5 us = 238.5 us
DIGITAL INPUT REGISTER (DIR)
Address 3F7 READ ONLY
This register is read-only in all modes.
PC-AT Mode
7
6
5
4
3
2
1
0
DSK
0
0
0
0
0
0
0
CHG
RESET
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
COND.
BIT 0 – 6 UNDEFINED
The data bus outputs D0 – 6 are read as ‘0’.
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value
programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).
PS/2 Mode
7
6
5
4
3
2
1
0
DSK
1
1
1
1
DRATE DRATE nHIGH
CHG
SEL1 SEL0 DENS
RESET
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
COND.
BIT 0 nHIGH DENS
This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are
selected.
SMSC DS – LPC47M192
Page 39
DATASHEET
Rev. 03/30/05