LPC47N227-MN View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
'LPC47N227-MN' PDF : 202 Pages View PDF
Table 32 - Register Summary for an Individual UART Channel (continued)
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Enable
Enable
0
0
0
0
Receiver Line MODEM
Status
Status
Interrupt
Interrupt
(ELSI)
(EMSI)
Interrupt ID Bit Interrupt ID Bit 0
0
FIFOs
FIFOs
(Note 5)
Enabled
Enabled
(Note 5)
(Note 5)
XMIT FIFO DMA Mode Reserved
Reserved
RCVR Trigger RCVR Trigger
Reset
Select (Note
LSB
MSB
6)
Number of
Parity Enable Even Parity Stick Parity Set Break
Divisor Latch
Stop Bits
(PEN)
Select (EPS)
Access Bit
(STB)
(DLAB)
OUT1
OUT2
Loop
0
0
0
(Note 3)
(Note 3)
Parity Error Framing Error Break
Transmitter Transmitter Error in RCVR
(PE)
(FE)
Interrupt (BI) Holding
Empty (TEMT) FIFO (Note 5)
Register
(Note 2)
(THRE)
Trailing Edge Delta Data
Clear to Send Data Set
Ring Indicator Data Carrier
Ring Indicator Carrier Detect (CTS)
Ready (DSR) (RI)
Detect (DCD)
(TERI)
(DDCD)
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Note 3: This bit no longer has a pin associated with it.
Note 4: When operating in the XT mode, this register is not available.
Note 5: These bits are always zero in the non-FIFO mode.
Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip.
Note 7: The UART1 and UART2 FCR’s are shadowed in the UART1 FIFO Control Shadow Register
(CR15) and UART2 FIFO Control Shadow Register (CR16).
83
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