LPC47N227-MN View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
'LPC47N227-MN' PDF : 202 Pages View PDF
HOST
CONNECTOR
1
2-9
10
11
12
13
14
15
16
17
Table 35 - Parallel Port Connector
PIN NUMBER
83
68-75
80
79
78
STANDARD
nSTROBE
PD<0:7>
nACK
BUSY
PE
EPP
nWrite
PData<0:7>
Intr
nWait
(User Defined)
77
SLCT
82
nALF
(User Defined)
nDatastb
81
nERROR
(User Defined)
66
nINIT
nRESET
67
nSLCTIN
nAddrstrb
ECP
nStrobe
PData<0:7>
nAck
Busy, PeriphAck(3)
PError,
nAckReverse(3)
Select
nAutoFd,
HostAck(3)
nFault(1)
nPeriphRequest(3)
nInit(1)
nReverseRqst(3)
nSelectIn(1,3)
(1) = Compatible Mode
(3) = High Speed Mode
Note: For the cable interconnection required for ECP support and the Slave Connector pin numbers,
refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993.
This document is available from Microsoft.
IBM XT/AT Compatible, Bi-Directional And EPP Modes
Data Port
ADDRESS OFFSET = 00H
The Data Port is located at an offset of '00H' from the base address. The data register is cleared at
initialization by RESET. During a WRITE operation, the Data Register latches the contents of the internal
data bus. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports.
During a READ operation in SPP mode, PD0 - PD7 ports are buffered (not latched) and output to the host
CPU.
Status Port
ADDRESS OFFSET = 01H
The Status Port is located at an offset of '01H' from the base address. The contents of this register are
latched for the duration of a read cycle. The bits of the Status Port are defined as follows:
BIT 0 TMOUT - TIME OUT
This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A
logic zero means that no time out error has occurred; a logic 1 means that a time out error has been
detected.
The means of clearing the TIMEOUT bit is controlled by the TIMEOUT_SELECT bit as follows. The
TIMEOUT_SELECT bit is located at bit 2 of CR21.
90
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