LPC47U332 View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

LPC47U332

100 Pin Enhanced Super I/O for LPC Bus with Consumer Features and SMBus Controller

SMSC -> Microchip 

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Configuration Control Register (CCR)

Address 3F7 WRITE ONLY

PC/AT and PS/2 Modes

7

6

5

4

3

2

1

0

0

0

0

0

0

0 DRATE DRATE

SEL1 SEL0

RESET N/A N/A N/A N/A N/A N/A

1

0

COND.

BIT 0 and 1 DATA RATE SELECT 0 and 1

These bits determine the data rate of the floppy controller. See Table 13 for the appropriate values.

BIT 2 - 7 RESERVED

Should be set to a logical "0".

PS/2 Model 30 Mode

7

6

5

4

3

2

1

0

0

0

0

0

0 NOPREC DRATE DRATE

SEL1 SEL0

RESET N/A N/A N/A N/A N/A

N/A

1

0

COND.

BIT 0 and 1 DATA RATE SELECT 0 and 1

These bits determine the data rate of the floppy controller. See Table 13 for the appropriate values.

BIT 2 NO PRECOMPENSATION

This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in

Model 30 register mode. Unaffected by software reset.

BIT 3 - 7 RESERVED

Should be set to a logical "0"

Table 14 shows the state of the DENSEL pin. The DENSEL pin is set high after a hardware reset and

is unaffected by the DOR and the DSR resets.

Status Register Encoding

During the Result Phase of certain commands, the Data Register contains data bytes that give the

status of the command just executed.

36

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