LPC47U332 View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
LPC47U332
SMSC -> Microchip
'LPC47U332' PDF : 252 Pages View PDF
The following paragraphs detail the operation of
the FIFO flow control. In these descriptions,
<threshold> is defined as the number of bytes
available to the FDC when service is requested
from the host and ranges from 1 to 16. The
parameter FIFOTHR, which the user programs,
is one less and ranges from 0 to 15.
A low threshold value (i.e. 2) results in longer
periods of time between service requests, but
requires faster servicing of the request for both
read and write cases. The host reads (writes)
from (to) the FIFO until empty (full), then the
transfer request goes inactive. The host must
be very responsive to the service request. This
is the desired case for use with a "fast" system.
A high value of threshold (i.e. 12) is used with a
"sluggish" system by affording a long latency
period after a service request, but results in
more frequent service requests.
Non-DMA Mode - Transfers from the FIFO to
the Host
The interrupt and RQM bit in the Main Status
Register are activated when the FIFO contains
(16-<threshold>) bytes or the last bytes of a full
sector have been placed in the FIFO. The FINT
pin can be used for interrupt-driven systems,
and RQM can be used for polled systems. The
host must respond to the request by reading
data from the FIFO. This process is repeated
until the last byte is transferred out of the FIFO.
The FDC will deactivate the interrupt and RQM
bit when the FIFO becomes empty.
Non-DMA Mode - Transfers from the Host to the
FIFO
The interrupt and RQM bit in the Main Status
Register are activated upon entering the
execution phase of data transfer commands.
The host must respond to the request by writing
data into the FIFO. The interrupt and RQM bit
remain true until the FIFO becomes full. They
are set true again when the FIFO has
<threshold> bytes remaining in the FIFO. The
FDC enters the result phase after the last byte is
taken by the FDC from the FIFO (i.e. FIFO
empty condition).
DMA Mode - Transfers from the FIFO to the
Host
The FDC generates a DMA request cycle when
the FIFO contains (16 - <threshold>) bytes, or
the last byte of a full sector transfer has been
placed in the FIFO. The DMA controller must
respond to the request by reading data from the
FIFO. The FDC will deactivates the DMA
request by generating the proper sync for the
data transfer, this occurs when the FIFO
becomes empty.
DMA Mode - Transfers from the Host to the
FIFO.
The FDC generates a DMA request cycle when
entering the execution phase of the data transfer
commands. The DMA controller must respond
by placing data in the FIFO. The DMA request
remains active until the FIFO becomes full. The
DMA request cycle is reasserted when the FIFO
has <threshold> bytes remaining in the FIFO.
The FDC terminates the DMA cycles after a TC,
indicating that no more data is required.
Data Transfer Termination
The FDC supports terminal count explicitly
through the TC cycle and implicitly through the
underrun/overrun and end-of-track (EOT)
functions. For full sector transfers, the EOT
parameter can define the last sector to be
transferred in a single or multi-sector transfer.
If the last sector to be transferred is a partial
sector, the host can stop transferring the data in
mid-sector, and the FDC will continue to
complete the sector as if a TC cycle was
received. The only difference between these
implicit functions and a TC cycle is that they
return "abnormal termination" result status.
Such status indications can be ignored if they
were expected.
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