LPC47U33X View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

LPC47U33X

100 Pin Enhanced Super I/O for LPC Bus with Consumer Features and SMBus Controller

SMSC -> Microchip 

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BIT 6 DIO

Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a

write is required.

BIT 7 RQM

Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0.

Data Register (FIFO)

Address 3F5 READ/WRITE

All command parameter information, disk data and result status are transferred between the host

processor and the floppy disk controller through the Data Register.

Data transfers are governed by the RQM and DIO bits in the Main Status Register.

The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT

hardware compatibility. The default values can be changed through the Configure command (enable

full FIFO operation with threshold control). The advantage of the FIFO is that it allows the system a

larger DMA latency without causing a disk error. Table 14 gives several examples of the delays with a

FIFO.

The data is based upon the following formula:

Threshold # x

1

x 8 - 1.5 µs = DELAY

DATA RATE

At the start of a command, the FIFO action is always disabled and command parameters must be

sent based upon the RQM and DIO bit settings. As the command execution phase is entered, the

FIFO is cleared of any data to ensure that invalid data is not transferred.

An overrun or underrun terminates the current command and the transfer of data. Disk writes will

complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to

remove the remaining data so that the result phase may be entered.

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