LPC47U33X View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

LPC47U33X

100 Pin Enhanced Super I/O for LPC Bus with Consumer Features and SMBus Controller

SMSC -> Microchip 

Prev 31 32 33 34 35 36 37 38 39 40 Next

DOR Reset vs. DSR Reset (Software Reset)

These two resets are functionally the same.

Both will reset the FDC core, which affects drive

status information and the FIFO circuits. The

DSR reset clears itself automatically while the

DOR reset requires the host to manually clear it.

DOR reset has precedence over the DSR reset.

The DOR reset is set automatically upon a pin

reset. The user must manually clear this reset

bit in the DOR to exit the reset state.

MODES OF OPERATION

The FDC has three modes of operation, PC/AT

mode, PS/2 mode and Model 30 mode. These

are determined by the state of the Interface

Mode bits in LD0-CRF0[3,2].

PC/AT mode

The PC/AT register set is enabled, the DMA

enable bit of the DOR becomes valid (controls

the interrupt and DMA functions), DENSEL is an

active high signal.

PS/2 mode

This mode supports the PS/2 models 50/60/80

configuration and register set. In this mode, the

DMA bit of the DOR becomes a "don't care."

The DMA and interrupt functions are always

enabled, DENSEL is an active high signal.

Model 30 mode

This mode supports PS/2 Model 30

configuration and register set the DMA enable

bit of the DOR becomes valid (controls the

interrupt and DMA functions), DENSEL is an

active low signal.

DMA Transfers

DMA transfers are enabled with the Specify

command and are initiated by the FDC by

asserting a DMA request cycle. DMA read, write

and verify cycles are supported. The FDC

supports two DMA data transfer modes: Single

Transfer and Burst Transfer. Burst mode is

enabled via Logical Device 0-CRF0-Bit[1]. (LD0-

CRF0[1])

Controller Phases

For simplicity, command handling in the FDC

can be divided into three phases: Command,

Execution, and Result. Each phase is described

in the following sections.

Command Phase

After a reset, the FDC enters the command

phase and is ready to accept a command from

the host. For each of the commands, a defined

set of command code bytes and parameter

bytes has to be written to the FDC before the

command phase is complete. (Please refer to

Table 19 for the command set descriptions).

These bytes of data must be transferred in the

order prescribed.

Before writing to the FDC, the host must

examine the RQM and DIO bits of the Main

Status Register. RQM and DIO must be equal

to "1" and "0" respectively before command

bytes may be written. RQM is set false by the

FDC after each write cycle until the received

byte is processed. The FDC asserts RQM again

to request each parameter byte of the command

unless an illegal command condition is

detected. After the last parameter byte is

received, RQM remains "0" and the FDC

automatically enters the next phase as defined

by the command definition.

The FIFO is disabled during the command

phase to provide for the proper handling of the

"Invalid Command" condition.

Execution Phase

All data transfers to or from the FDC occur

during the execution phase, which can proceed

in DMA or non-DMA mode as indicated in the

Specify command.

After a reset, the FIFO is disabled. Each data

byte is transferred by a read/write or DMA cycle

depending on the DMA mode. The Configure

command can enable the FIFO and set the

FIFO threshold value.

40

Share Link: