LPC61W492QFP View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
LPC61W492QFP
SMSC -> Microchip
'LPC61W492QFP' PDF : 160 Pages View PDF
FDC FUNCTIONAL DESCRIPTION
LPC61W492 FDC
The floppy disk controller of the LPC61W492 integrates all of the logic required for floppy disk control.
The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible
values. The FIFO provides better system performance in multi-master systems. The digital data
separator supports up to 2 M bits/sec data rate. The FDC includes the following blocks: AT interface,
Precompensation, Data Rate Selection, Digital Data Separator, FIFO, and FDC Core.
AT Interface
The interface consists of the standard asynchronous signals: nRD, nWR, A0-A3, IRQ, DMA control,
and a data bus. The address lines select between the configuration registers, the FIFO and
control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal
modes. The PS/2 register sets are a superset of the registers found in a PC/AT.
FIFO (Data)
The FIFO is 16 bytes in size and has programmable threshold values. All command parameter
information and disk data transfers go through the FIFO. Data transfers are governed by the RQM and
DIO bits in the Main Status Register.
The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware
compatibility. The default values can be changed through the CONFIGURE command. The advantage
of the FIFO is that it allows the system a larger DMA latency without causing disk errors. The following
tables give several examples of the delays with a FIFO. The data are based upon the following formula:
THRESHOLD # & (1/DATA/RATE) *8 - 1.5 'S = DELAY
FIFO THRESHOLD
MAXIMUM DELAY TO SERVICING AT 500KBPS
Data Rate
1 Byte
1 & 16 'S - 1.5 'S = 14.5 'S
2 Byte
2 & 16 'S - 1.5 'S = 30.5 'S
8 Byte
8 & 16 'S - 1.5 'S = 6.5 'S
15 Byte
15 & 16 'S - 1.5 'S = 238.5 'S
FIFO THRESHOLD
MAXIMUM DELAY TO SERVICING AT 1MBPS
Data Rate
1 Byte
1 & 8 'S - 1.5 'S = 6.5 'S
2 Byte
2 & 8 'S - 1.5 'S = 14.5 'S
8 Byte
8 & 8 'S - 1.5 'S = 62.5 'S
15 Byte
15 & 8 'S - 1.5 'S = 118.5 'S
At the start of a command the FIFO is always disabled and command parameters must be sent based
upon the RQM and DIO bit settings in the main status register. When the FDC enters the command
execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred.
An overrun and underrun will terminate the current command and the data transfer. Disk writes will
complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to
remove the remaining data so that the result phase may be entered.
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