LPC61W492QFP View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

LPC61W492QFP

Integrated Super I/O Controller for LPC Bus with Game and MIDI Ports/Plus Hardware Monitoring Functions

SMSC -> Microchip 

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Command

The microprocessor issues all required information to the controller to perform a specific operation.

Execution

The controller performs the specified operation.

Result

After the operation is completed, status information and other housekeeping information is provided to

the microprocessor.

FDC Commands

Command Symbol Descriptions:

C:

Cylinder number 0 - 256

D:

Data Pattern

DIR:

Step Direction

DIR = 0, step out

DIR = 1, step in

DS0:

Disk Drive Select 0

DS1:

Disk Drive Select 1

DTL:

Data Length

EC:

Enable Count

EOT:

End of Track

EFIFO:

Enable FIFO

EIS:

Enable Implied Seek

EOT:

End of track

FIFOTHR:

FIFO Threshold

GAP:

Gap length selection

GPL:

Gap Length

H:

Head number

HDS:

Head number select

HLT:

Head Load Time

HUT:

Head Unload Time

LOCK:

Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset

MFM:

MFM or FM Mode

MT:

Multitrack

N:

The number of data bytes written in a sector

NCN:

New Cylinder Number

ND:

Non-DMA Mode

OW:

Overwritten

PCN:

Present Cylinder Number

POLL:

Polling Disable

PRETRK:

Precompensation Start Track Number

R:

Record

RCN:

Relative Cylinder Number

R/W:

Read/Write

SC:

Sector/per cylinder

SK:

Skip deleted data address mark

SRT:

Step Rate Time

ST0:

Status Register 0

ST1:

Status Register 1

ST2:

Status Register 2

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