LRS13023 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS13023' PDF : 61 Pages View PDF
SHARP
LRS13023
20
JO Clear Block Lock-Bits Command
J set block lock-bits are cleared in parallel via the
Iear Block Lock-Bits command. With the master
)&bit not set, block lock-bits can be cleared using
nly the Clear Block Lock-Bits command. If the master
>ck-bit is set, clearing block lock-bits requires both the
Ilear Block Lock-Bits command and V, on the m
lin. See Table 6 for a summary of hardware and
oftware write protection options.
Ilear block lock-bits operation is executed by a
No-cycle command sequence. A clear block lock-bits
etup is first written. After the command is written,
le device automatically outputs status register data
fhen read (see Figure 9). The CPU can detect
ompletion of the clear block lock-bits event by
nalyzing status register bit SR7.
Vhen the operation is complete, status register bit
R5 should be checked. If a clear block lock-bit error is
.etected, the status register should be cleared. The
XJI will remain in read status register mode until
nother command is issued.
accidentally cleared. An invalid Clear Block Lock-Bits
command sequence will result in status register bits
SR.4 and SR5 being set to “1”. Also, a reliable clear
block lock-bits operation can only occur when
Vcc=VccI and VPP=VPP,. If a clear block lock-bits
operation is attempted while V+V,,,
SR.3 and
SR.5 will be set to “1”. In the absence of this high
voltage, the block lock-bits content are protected
against alteration. A successful clear block lock-bits
operation requires that the master lock-bit is not set or,
if the master lock-bit is set, that m=V,.
If it is
attempted with the master lock-bit set and i?is=VIH,
SR.1 and SR.5 will be set to “1” and the operation will
fail. A clear block lock-bits operation with VI&@
<V, produce spurious results and should not be
attempted.
If a clear block lock-bits operation is aborted due to
VP, or Vcc transitioning out of valid range or Rp
active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-bits is
required to initialize block lock-bit contents to known
values. Once the master lock-bit is set, it cannot be
cleared.
his two-step sequence of set-up followed by
xecution ensures that block lock-bits are not
Operation
Block Erase or
Byte Write
Set Block
Lock-Bit
Set Master
Lock-Bit
Clear Block
Lock-Bits
Master
Lock-Bit
X
0
1
X
0
1
Table 6. Write Protection Alternatives
Block
Lock-Bit
RF
Effect
0
Vw, . or
Block Erase and Byte Write Enabled
VW
1
VTW
Block is Locked. Block Erase and Byte Write Disabled
VHH
Block Lock-Bit Override. Block Erase and Byte Write
Enabled
X
V, or
Set Block Lock-Bit Enabled
VW
X
VW
Master Lock-Bit is Set. Set Block Lock-Bit Disabled
.v,
Master Lock-Bit Override. Set Block Lock-Bit Enabled
X
V,,
Set Master Lock-Bit Disabled
VW
Set Master Lock-Bit Enabled
X
V-,. or
Clear Block Lock-Bits Enabled
VW
X
V,,
Master Lock-Bit is Set. Clear Block Lock-Bits Disabled
VHH
Master Lock-Bit Override. Clear Block Lock-Bits
Share Link: 
