LRS13023 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS13023' PDF : 61 Pages View PDF
_____SHARP
LRS13023
5 DESIGN CONSIDERATIONS
i.1 Three-Line Output Control
The device will often be used in large memory arrays.
SHARPprovides three control inputs to accommodate
nultiple memory connections. Three-line control
xovides for:
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention wilI
not occur.
To use these control inputs efficiently, an address
iecoder should enable m while m should be
:onnected to all memory devices and the system’s
READ control line. This assures that only selected
nemory devices have active outputs while deselected
nemory devices are in standby mode. y should be
:onnected to the system POWERGOOD signal to
prevent unintended writes during system power
ran&ions. POWERGOOD should also toggle during
system reset.
i.2 Power Supply Decoupling
?ash memory power switching characteristics require
:areful device decoupling. System designers are
nterested in three supply current issues; standby
urrent levels, active current levels and transient peaks
rroduced by falling and rising edges of m and m.
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection will
suppress transient voltage peaks. Each device shouId
have a 0.1 uF ceramic capacitor connected between its
V,, and GND and between its V,, and GND. These
high-frequency, low inductance capacitors should be
placed as close as possible to package leads.
Additionally, for every eight devices, a 4.7 pF
electrolytic capacitor should be placed at the array’s
power supply connection between Vc- and GND. The
bulk capacitor will overcome voltage slumps caused
by PC board &ace inductance.
5.3 V,, Trace on Printed Circuit Boards
Updating flash memories that reside in the target
system requires that the printed circuit board designer
pay attention to the V,, Power supply trace. The V,,
pin supplies the memory cell current for byte writing
and block erasing. Use similar trace widths and layout
considerations given to the V,, power bus. Adequate
V, supply traces and decoupling will decrease V,,
voltage spikes and overshoots.
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