LRS1383 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1383' PDF : 114 Pages View PDF
FUM00701
3
that a burst is in progress. The synchronous burst feature
cannot cross partition boundaries.
The LH28F320BX/LH28F640BX series contains a page
buffer of 16-word 2 plane. In the page buffer program
mode, the data to be programmed is first stored into the
page buffer before being transferred to the memory array.
A page buffer program has high speed program
performance. The page buffer program operation
programs up to 16 word 2 data at sequential addresses
within one block. That is, this operation cannot be used to
program data at addresses separated by something even in
the same block, or divided into different blocks. Page
buffer program cannot be applied to OTP block described
later in this section.
For the parameter blocks and main blocks, individual
block locking scheme that allows any block to be locked,
unlocked or locked-down with no latency. The time
required for block locking is less than the minimum
command cycle time (minimum time from the rising edge
of CE# or WE# to write the command to the next rising
edge of CE# or WE#). The block is locked via the Set
Block Lock Bit command or Set Block Lock-down bit
command. Block erase, full chip erase and (page buffer)
program operation cannot be executed for locked block,
to protect codes and data from unwanted operation due to
noises, etc. When the WP# pin is at VIL, the locked-down
block cannot be unlocked. When WP# pin is at VIH, lock-
down bits are disabled and any block can be locked or
unlocked through software. After WP# goes VIL, any
block previously marked lock-down revert to that state.
At power-up or device reset, all blocks default to locked
state and are not locked-down, regardless of the states
before power-off or reset operation. This means that all
write operations on any block are disabled.
Unauthorized use of cellular phone, communication
device, etc. can be avoided by storing a security code into
the 8-word OTP (One Time Program) block (see Figure
4) provided in addition to the parameter and main blocks.
To ensure high reliability, a lock function for the OTP
block is provided.
The LH28F320BX/LH28F640BX series has a VPP pin
which monitors the level of the power supply voltage.
When VPP VPPLK, memory contents cannot be altered
and the data in all blocks are completely write protected
(see Note 1). Note that the VPP is used only for checking the
supply voltage, not used for device power supply pin.
Automatic Power Savings (APS) is the low power
features to help increase battery life in portable
applications. APS mode is initiated shortly after read
cycle completion. In this mode, its current consumption
decreases to the value equivalent of that in the standby
mode. Standard address access timings (tAVQV) provide
new data when addresses are changed. During dual work
operation (one partition being erased or programmed,
while other partitions are read modes), the device cannot
enter the Automatic Power savings mode if the input
address remains unchanged.
A CUI (Command User Interface) serves as the interface
between the system processor and internal operation of
the device. A valid command sequence written to the CUI
initiates device automation. LH28F320BX/LH28F640BX
series uses an advanced WSM (Write State Machine) to
automatically execute erase and program operations
within the memory array. The WSM is controlled through
the CUI. By writing a valid command sequence to the
CUI, the WSM is instructed to automatically handle the
sequence of internal events and timings required to block
erase, full chip erase, (page buffer) program or OTP
program operations.
Status registers are prepared for each partition to indicate
the status of the partition. Even if the WSM is occupied
by executing erase or program operation in one partition,
the status register of other partition reports that the device
is not busy when the device is set to 2, 3 or 4 partitions
configuration.
When the RST# pin is at VIL, reset mode is enabled
which minimizes power consumption and provides write
protection. The RST# is also useful for resetting the
WSM to read array mode and initializing the status
register bits to "80H". During power-on/off or transitions,
keep the RST# pin at VIL level to protect the data from
noises, and initialize the device’s internal control circuit.
(Note 1) Please note following:
• For the lockout voltage VPPLK to inhibit all write
functions, refer to specifications.
• VPP should be kept lower than VPPLK (GND) during
read operations to protect the data in all blocks.
Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 March 1, 2001
Rev. 2.20
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