LRS1383 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1383' PDF : 114 Pages View PDF
FUM00701
6
Symbol
A0-A20
A0-A21
DQ0-DQ15
CE#
CLK
ADV#
RST#
OE#
WE#
WP#
WAIT#
Type
INPUT
INPUT
INPUT/
OUTPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
Table 3.1. Pin Descriptions
Name and Function
ADDRESS INPUTS: Inputs for addresses. 32M: A0-A20
ADDRESS INPUTS: Inputs for addresses. 64M: A0-A21
DATA INPUT/OUTPUTS: Inputs data and commands during CUI (Command User
Interface) write cycles, outputs data during memory array, status register, query,
identifier code and device configuration code reads. Data pins float to high-impedance
(High Z) when the chip or outputs are deselected. Data is internally latched during an
erase or program cycle.
Chip Enable: Activates the device’s control logic, input buffers, decoders and sense
amplifiers. CE#-high (VIH) deselects the device and reduces power consumption to
standby levels.
CLOCK: Synchronizes the memory to the system bus operating frequency in
synchronous burst mode. The first rising (or falling if RCR.6 is "0") edge latches the
address when ADV# is VIL or upon a rising ADV# edge. This is used only for
synchronous burst mode.
ADDRESS VALID: Addresses are input to the memory when ADV# is low (VIL).
Addresses are latched on ADV#’s rising edge during read and write operations.
RESET: When low (VIL), RST# resets internal automation and inhibits write operations
which provides data protection. RST#-high (VIH) enables normal operation. After
power-up or reset mode, the device is automatically set to asynchronous read array
mode. RST# must be low during power-up.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of CE# or WE# (whichever goes high first).
WRITE PROTECT: When WP# is VIL, locked-down blocks cannot be unlocked. Erase
or program operation can be executed to the blocks which are not locked and locked-
down. When WP# is VIH, lock-down is disabled.
WAIT: Outputs data valid status in synchronous burst mode while OE# is asserted.
When high (VOH) during a burst mode, data is valid. WAIT# low (VOL) indicates invalid
data. WAIT# is pulled high (VOH) by an internal resister. The WAIT# signals of the
multiple devices can be tied together to drive one system WAIT# signal. WAIT# is used
only for synchronous burst mode. It also works during a continuous burst mode or 4-, 8-
word burst with no-wrap (RCR.3="1") mode
Synchronous burst mode will be available for future device.
Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 March 1, 2001
Rev. 2.20
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