LRS1383 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1383' PDF : 114 Pages View PDF
FUM00701
14
2 Principles of Operation
Synchronous/Page Mode Dual Work Flash memory
LH28F320BX/LH28F640BX series includes an on-chip
WSM (Write State Machine) and can automatically
execute block erase, full chip erase, (page buffer)
program or OTP program operation after writing the
proper command to the CUI (Command User Interface).
2.1 Operation Mode after Power-up or Reset
Mode
After initial power-up or reset mode (refer to Bus
Operation in Section 3), the device defaults to the
following mode.
• Asynchronous read mode in which 8-word page mode
is available
• Plane 0-2 are merged into one partition for top
parameter devices and plane1-3 are merged into one
partition for bottom parameter devices.
• All blocks default to locked state and are not locked-
down.
Manipulation of external memory control pins (CE#,
OE#) allow read array, standby and output disable modes.
2.2 Read, Program and Erase Operation
Independent of the VPP voltage, the memory array, status
register, identifier codes, OTP block and query codes can
be accessed. And also, set/clear block lock configuration,
set read configuration register and set partition
configuration register are available even if the VPP
voltage is lower than VPPLK. Applying the specified
voltage on VCC and VPPH1/2 on VPP enables successful
block erase, full chip erase, (page buffer) program and
OTP program operation. All functions associated with
altering memory contents, which is block erase, full chip
erase, (page buffer) program and OTP program, are
accessed via the CUI and verified through the status
register.
Commands are written using standard microprocessor
write timings. Addresses and data are internally latched
on the rising edge of CE# or WE# whichever goes high
first during command write cycles. The CUI contents
serve as input to the WSM, which controls block erase,
full chip erase, (page buffer) program and OTP program.
The internal algorithms are regulated by the WSM,
including pulse repetition, internal verification and
margining of data. Writing the appropriate command
outputs array data, status register data, identifier codes,
lock configuration codes, device configuration codes,
data within the OTP block and query codes.
In any block, the user can store an interface software that
initiates and polls progress of block erase or (page buffer)
program. Because the LH28F320BX/LH28F640BX
series has dual work function, data can be read from the
partition not being erased or programmed without using
the block erase suspend or (page buffer) program
suspend. When the target partition is being erased or
programmed, block erase suspend or (page buffer)
program suspend allows system software to read/program
data from/to blocks other than that which is suspended.
2.3 Status Register for Each Partition
The LH28F320BX/LH28F640BX series has status
registers for each partition. The 8-bit status register is
available to monitor the partition state, or the erase or
program status. Status Register indicates the status of the
partition, not WSM. Even if the status register bit SR.7 is
"1", the WSM may be occupied by the other partition
when the device is set to 2, 3 or 4 partitions configuration.
The status register reports if an erase or program
operation to each partition has been successfully
completed, and if not, indicates a reason for the error.
This register cannot be set, only can be cleared by writing
the Clear Status Register command or by resetting the
device.
2.4 Data Protection
Block lock bit and block lock-down bit can be set for each
block, to protect the data within its block.
If the RST# is driven low (VIL), or if the voltage on the
VCC pin is below the write lock out voltage (VLKO), or if
the voltage on the VPP pin is below the write lock out
voltage (VPPLK), then all write functions including OTP
program are disabled.
The system should be designed to switch the voltage on
VPP below the write lock out voltage (VPPLK) for read
cycles. This scheme provides the data protection at the
hardware level. The two-cycle command sequence
architecture for block erase, full chip erase, (page buffer)
program, OTP program, and block lock configuration
provides the data protection at the software level against
data alternation.
Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 March 1, 2001
Rev. 2.20
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