LS7566 View Datasheet(PDF) - LSI Corporation
Part Name
Description
MFG CO.
'LS7566' PDF : 13 Pages View PDF
MDR0 (x0MDR0, x1MDR0, x2MD0, x3MDR0): The MDR0 is an 8-bit read/write register which configures the counting
modes and the index input functionality. Upon power-up, the MDR0 is cleared to zero.
MDR0: B7 B6 B5 B4 B3 B2 B1 B0
B1B0 = 00: Non-quadrature count mode (A = clock, B = direction).
= 01: x1 quadrature count mode (one count per quadrature cycle).
= 10: x2 quadrature count mode (two counts per quadrature cycle).
= 11: x4 quadrature count mode (four counts per quadrature cycle).
B3B2 = 00: Free-running count mode.
= 01: Single-cycle count mode (CNTR disabled with carry and borrow, re-enabled with reset or load)
= 10: Range-limit count mode (up and down count ranges are limited between PR and zero, respectively.
Counting freezes at these limits but resumes when the direction is reversed)
= 11: Modulo-n count mode (input count clock frequency is divided by a factor of [n+1], where n = PR. In
up direction, the CNTR is cleared to 0 at CNTR = PR and up count continues. In down direction, the
CNTR is preset to the value of PR at CNTR = 0 and down count continues. A mod-n rollover marker
pulse is generated at each limit at the FLGa output).
B5B4 = 00: Disable INDX input.
= 01: Configure INDX input as the load CNTR input (transfers PR to CNTR).
= 10: Configure INDX as the reset_CNTR input (clears CNTR to 0).
= 11: Configure INDX as the load_OL input (transfers CNTR to OL).
B6 = 0: Negative INDX input.
= 1: Positive INDX input.
B7 = 0: Input filter clock (PCK) division factor = 1. Filter clock frequency = fPCK.
= 1: Input filter clock division factor = 2. Filter clock frequency = fPCK/2.
MDR1 (x0MDR1, x1MDR1, x2MD1, x3MDR1): The MDR1 is an 8-bit read/write register which configures the FLGa and
FLGb output functionality. In addition, the MDR1 can be used to enable/disable counting. Upon power-up, the MDR1 is
cleared to zero:
MDR1: B7 B6 B5 B4 B3 B2 B1 B0
B0 = 1: Enable Carry on FLGa (flags CNTR overflow; latched or unlatched logic low on carry).
B1 = 1: Enable Borrow on FLGa (flags CNTR underflow, latched or unlatched logic low on borrow).
B2 = 1: Enable Compare on FLGa (In free-running count mode, a latched or unlatched logic low is generated in both
up and down count directions at CNTR = PR. In contrast, in range-limit and mod-n count modes a latched or
unlatched low is generated at CNTR = PR in the up-count direction only. Also, in these two modes in the
down-count direction, a latched or unlatched low is generated when the CNTR underflows. (See NOTE 2)
B3 = 1: Enable index on FLGa (flags index, latched or unlatched logic low when INDX input is at active level)
B5B4 = 00: FLGb disabled (fixed high)
= 01: FLGb = Sign, high for negative signifying CNTR underflow, low for positive.
= 10: FLGb = Up/Down count direction, high in count-up, low in count-down.
B6 = 0: Enable counting.
= 1: Disable counting.
B7 = 0: FLGa is latched. (See NOTE 2)
= 1: FLGa is non-latched and instantaneous.
NOTE 1: Carry, Borrow, Compare and Index can all be simultaneously enabled on FLGa.
NOTE 2: In mod-n or range-limit modes, if Compare output is enabled on FLGa,
instantaneous (non-latched) Compare signals are generated at PR = CNTR in up-count mode and
instantaneous Borrow signals are generated at CNTR = 0 in down-count mode, independent of the states of B7.
Carry and Borrow signals on FLGa remain unaffected in these two modes. Consequently, a latched Carry or Index state
willblock the instantaneous Compare and Borrow clocks. It is recommended that only non-latched Flag mode is used in
the mod-n and range-limit modes if carry and index signals are enablrd on FLGa as well in these two modes.
7566-032305-4
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