RD
CS
RS
CHS
DB
tr1
tr10
tr2
tr3
tr4
tr5
tr6
tr7
tr8
tr9
VALID
DATA
FIGURE 2. READ CYCLE
VALID DATA
WR
CS
RS
CHS
DB
tw1
tw2
tw4
tw3
tw5
tw6
tw7
tw8
tw9
INPUT DATA
tw10
INPUT DATA
FIGURE 3. WRITE CYCLE
PCK
f f (Note 4)
(MDR0 <7> = 0)
f f (Note 4)
(MDR0 <7> = 1)
A
B
INDX
t1
t2
t3
t3
t5
t4
t4
t ih
t is
Note 1
t id
t5
t4
t4
t is
t ih
Note 2
Note 1. Positive index coincident with both A and B high.
Note 2. Positive index coincident with both A and B low.
Note 3. The index logic level in the above examples are inverted for negative index.
Note 4. fF is the internal effective filter clock.
FIGURE 4. PCK, A, B and INDX
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