LT3971 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LT3971' PDF : 24 Pages View PDF
LT3971/LT3971-3.3/LT3971-5
APPLICATIONS INFORMATION
D4
MBRS140
VIN
VIN
BOOST
EN
SW
LT3971
BD
GND
FB
VOUT
+
BACKUP
3971 F07
Figure 8. Diode D4 Prevents a Shorted Input from Discharging a
Backup Battery Tied to the Output. It Also Protects the Circuit from
a Reversed Input. The LT3971 Runs Only When the Input is Present
PCB Layout
For proper operation and minimum EMI, care must be taken
during printed circuit board layout. Figure 9 shows the
recommended component placement with trace, ground
plane and via locations. Note that large, switched currents
flow in the LT3971’s VIN and SW pins, the catch diode
(D1), and the input capacitor (C1). The loop formed by
these components should be as small as possible. These
components, along with the inductor and output capacitor,
should be placed on the same side of the circuit board,
and their connections should be made on that layer. Place
a local, unbroken ground plane below these components.
The SW and BOOST nodes should be as small as possible.
Finally, keep the FB and RT nodes small so that the ground
traces will shield them from the SW and BOOST nodes.
The Exposed Pad on the bottom of the package must be
soldered to ground so that the pad acts as a heat sink. To
keep thermal resistance low, extend the ground plane as
much as possible, and add thermal vias under and near
the LT3971 to additional ground planes within the circuit
board and on the bottom side.
Hot Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of LT3971 circuits. However, these ca-
pacitors can cause problems if the LT3971 is plugged into
a live supply. The low loss ceramic capacitor, combined
with stray inductance in series with the power source,
forms an under damped tank circuit, and the voltage at
L1
VOUT
C2
C3
D1
C1
RPG
C4
GND
RT
R2
C5
R1
GND
VIAS TO LOCAL GROUND PLANE
VIAS TO VOUT
VIAS TO SYNC
VIAS TO RUN/SS
VIAS TO PG
VIAS TO VIN
3971 F09
OUTLINE OF LOCAL
GROUND PLANE
Figure 9. A Good PCB Layout Ensures Proper, Low EMI Operation
the VIN pin of the LT3971 can ring to twice the nominal
input voltage, possibly exceeding the LT3971’s rating and
damaging the part. If the input supply is poorly controlled
or the user will be plugging the LT3971 into an energized
supply, the input network should be designed to prevent
this overshoot. See Linear Technology Application Note
88 for a complete discussion.
High Temperature Considerations
For higher ambient temperatures, care should be taken in
the layout of the PCB to ensure good heat sinking of the
LT3971. The Exposed Pad on the bottom of the package
must be soldered to a ground plane. This ground should be
tied to large copper layers below with thermal vias; these
layers will spread heat dissipated by the LT3971. Placing
additional vias can reduce thermal resistance further. The
maximum load current should be derated as the ambient
temperature approaches the maximum junction rating.
Power dissipation within the LT3971 can be estimated by
calculating the total power loss from an efficiency measure-
ment and subtracting the catch diode loss and inductor
3971fd
19
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