LT3992EFE View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LT3992EFE' PDF : 36 Pages View PDF
LT3992
Applications Information
Table 2. Efficiency and Size Comparisons for Different RRT/SYNC Values, 3.3V Output
FREQUENCY (kHz) RT/SYNC (kΩ)
EFFICIENCY
VVIN1/2 = 12V (%)
VIN(MAX) (V)†
L (µH)*
250
5.90
88
60
15
500
13.0
87
43
8.2
1000
28.0
84
21
3.3
1500
44.2
82
14
2.2
2250
69.8
78
9
1
† VIN(MAX) is defined as the highest typical input voltage that maintains constant output voltage ripple.
* Inductor and capacitor values chosen for stability and constant ripple current.
C (µF)*
120
60
30
22
15
C + L (Area, mm2)
59.8
54.6
51.9
46.9
19.1
The following example along with the data in Table 2
illustrates the trade-offs of switch frequency selection for
a single input voltage system.
Example:
VIN = 25V, VOUT = 3.3V, IOUT = 2A, tON(MIN) = 180ns,
VD = 0.6V, VSW = 0.4V.
Max
Frequency =
3.3+ 0.6
25 – 0.4+ 0.6
•1
180ns
~ 850kHz
RT/SYNC ~ 23.2kΩ (Figure 2 )
Input Voltage Range
Once the switching frequency has been determined, the
input voltage range of the regulator can be determined. The
minimum input voltage is determined by either the LT3992’s
minimum operating voltage of ~2.9V, or by its maximum duty
cycle. The duty cycle is the fraction of time that the internal
switch is on during a clock cycle. Unlike most fixed frequency
regulators, the LT3992 will not switch off at the end of each
clock cycle if there is sufficient voltage across the boost
capacitor (C3 in Figure 1) to fully saturate the output switch.
tP
SW1
Forcing switch off for a minimum time will only occur at the
end of a clock cycle when the boost capacitor needs to be
recharged. This operation has the same effect as lowering the
clock frequency for a fixed off time, resulting in a higher duty
cycle and lower minimum input voltage. The resultant duty
cycle depends on the charging times of the boost capacitor
and can be approximated by the following equation:
DCMAX
=
1
1+
1
B
where B is 3A divided by the typical boost current from
the Electrical Characteristics table.
This leads to a minimum input voltage of:
VIN(MIN)
=
VOUT + VD
DCMAX
–
VD
+
VSW
where VSW is the voltage drop of the internal switch.
Figure 4 shows a typical graph of minimum input voltage
vs load current for the 3.3V output shown in Figure 15.
6
VOUT = 3.3V
5
START-UP
4
RUNNING
tP/2
tP
SW2
CLKOUT
tP/2
tP
tDCLKOSW1
tDCLKOSW2
3992 F03
Figure 3. Timing Diagram RT/SYNC = 28.0k, tP = 1µs, VDIV = 0V
3
2
1
0
0 500 1000 1500 2000 2500 3000 3500
CURRENT (mA)
3992 F04
Figure 4. Minimum Input Voltage vs Load Current
3992fa
For more information www.linear.com/LT3992
13
Share Link: 
