LTC1066-1 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC1066-1
Linear Technology
'LTC1066-1' PDF : 20 Pages View PDF
LTC1066-1
APPLICATIONS INFORMATION
DC PERFORMANCE
The DC performance of the LTC1066-1 is dictated by the
DC characteristics of the input precision op amp.
1. DC input voltages in the vicinity of the filter’s half of the
total power supply are processed with exactly 0dB (or
1V/ V) of gain.
2. The typical DC input voltage ranges are equal to:
VIN = ±5.8V, VS = ±7.5V
VIN = ±3.6V, VS = ±5V
VIN = ±1.4V, VS = ±2.5V
With an input DC voltage range of VIN = ±5V, (VS =
±7.5V), the measured CMRR was 100dB. Figure 1
shows the DC gain linearity of the filter exceeding the
requirements of a 14-bit, 10V full scale system.
3. The filter output DC offset VOS(OUT) is measured with the
input grounded and with dual power supplies. The
VOS(OUT) is typically ±0.1mV and it is optimized for the
filter connection shown in the test circuit figure. The
filter output offset is equal to:
VOS(OUT) = VOS (op amp A) –IBIAS × RF = 0.1mV (Typ)
4. The VOS(OUT) temperature drift is typically 7µV/°C
(TA > 25°C), and – 7µV/°C (TA < 25°C).
5. The VOS(OUT) temperature drift can be improved by
using an input resistor RIN equal to the feedback resis-
tor RF, however, the absolute value of VOS(OUT) will
increase. For instance, if a 20k resistor is added in series
with pin 3 (see Test Circuit), the output VOS drift will be
75
VS = ±7.5V
50
TA = 25°C
fCLK = 1MHz
25
fC = 20kHz
0
–25
–50
–75
–100
–125
–6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6
INPUT VOLTAGE (VDC)
1066-1 F01
Figure 1. DC Gain Linearity
10
improved by 2µV/°C to 3µV/°C, however, the VOS(OUT)
may increase by 1mV(MAX).
6. The filter DC output offset voltage VOS(OUT) is indepen-
dent from the filter clock frequency (fCLK ≤ 250kHz).
Figures 2 and 3 show the VOS(OUT) variation for three
different power supplies and for clock frequencies up to
5MHz. Both figures were traced with the LTC1066-1
soldered into the PC board. Power supply decoupling is
very important, especially with ±7.5V supplies. If nec-
essary connect a small resistor (20Ω) between pins 5
and 18, and between pins 10 and 4, to isolate the
precision op amp supply pin from the switched
capacitor network supply (see the Test Circuit).
0.2
0.1
0
VS = ±2.5V
VS = ±5V
–0.1
–0.2
–0.3
–0.4
VS = ±7.5V
–0.5
–0.6 LINEAR PHASE
–0.7
TA = 25°C
fCLK/fC = 100:1
–0.8
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
CLOCK FREQUENCY (MHz)
1066-1 F02
Figure 2. Output Offset Change vs Clock
(Relative to Offset for fCLK = 250kHz)
0.2
0
VS = ±2.5V
VS = ±5V
–0.2
–0.4
–0.6
VS = ±7.5V
–0.8
–1.0 TA = 25°C
fCLK/fC = 50:1
–1.2
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
CLOCK FREQUENCY (MHz)
1066-1 F03
Figure 3. Output Offset Change vs Clock
(Relative to Offset for fCLK = 250kHz)
10661fa
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