BLOCK DIAGRA
LTC1066-1
RF
CF
2
–IN A
3
+IN A
–
HIGH SPEED
OP AMP
+
1
OUT A
V+ V– GND 50/100 CLK
5,18 4,10 15 8 9
LTC1066-1
14
FILTERIN
CONNECT 1
6
8TH ORDER
SWITCHED-
CAPACITOR
NETWORK
11 COMP1
13 COMP2
12
CONNECT 2
7
FILTEROUT
16
+IN B
–
HIGH SPEED
OP AMP
+
17
OUT B
PATENT PENDING
11066-1 BD
TEST CIRCUIT
20Ω
V–
1µF
VIN
0.1µF
V+
0.1µF
ELLIPTIC
RESPONSE
V+
50:1
10k
LINEAR PHASE
RESPONSE
100:1
fCLK
(DUTY CYCLE
= 50% ±10%)
20k
1
OUT A
V+ 18
2 –IN A
17
OUT B
3 +IN A
+IN B 16
4 V–
LTC1066-1 GND 15
5 V+
14
FILTERIN
6 CONNECT 1
COMP 2 13
7
FILTEROUT
8
50/100
CONNECT 2 12
11
COMP 1
9 CLK
V– 10
VOUT
20Ω
V+
0.1µF
NOTE: RC COMPENSATION BETWEEN PINS 11 AND 13 IS
REQUIRED ONLY FOR CLOCK-TUNABLE OPERATION FOR:
50kHz < fCUTOFFs ≤ 100kHz.
15pF
THE TEST SPECIFICATIONS FOR:
fCLK = 2MHz, fCUTOFF = 40kHz, AND
fCLK = 4MHz, fCUTOFF = 80kHz
INCLUDE THE EFFECTS OF RC COMPENSATION.
30k
V–
0.1µF
COMPENSATION DOES NOT INFLUECE THE SPECIFICATIONS
FOR:
fCLK = 400kHz, fCUTOFF = 8kHz.
FOR CLOCK-TUNABLE fCUTOFFs FROM 2kHz TO 50kHz
COMPENSATION IS NOT REQUIRED AND THE FILTER’S
PASSBAND PERFORMANCE IS REPRESENTED BY THE
TYPICAL SPECIFICATIONS AT:
fCLK = 400kHz, fCUTOFF = 8kHz.
1066-1 TC01
10661fa
9