LTC1272-3ACS View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1272-3ACS' PDF : 20 Pages View PDF
LTC1272
APPLICATI S I FOR ATIO
There are two modes of operation as outlined by the timing
diagrams of Figures 13 to 17. Slow Memory Mode is
designed for microprocessors which can be driven into a
Wait state, a Read operation brings CS and RD low which
initiates a conversion and data is read when conversion is
complete.
The second is the ROM Mode which does not require
microprocessor Wait states. A Read operation brings CS
and RD low which initiates a conversion and reads the
previous conversion result.
LTC1272
HBEN 19
CS 21
RD 20
5V
D
Q
FLIP
FLOP
CLEAR
CONVERSION START
(RISING EDGE TRIGGER)
BUSY
ACTIVE HIGH
ACTIVE HIGH
ENABLE THREE-STATE OUTPUTS
D11....D0/8 = DB11....DB0
ENABLE THREE-STATE OUTPUTS
D11....D8 = DB11....DB8
D7....D4 = LOW
D3/11....D0/8 = DB11....DB8
D11....D0/8 ARE THE ADC DATA OUTPUT PINS
DB11....DB0 ARE THE 12-BIT CONVERSION RESULTS
LTC1272 • TA14
Figure 12. Internal Logic for Control Inputs CS, RD and HBEN
CS & RD
t2
BUSY
tCONV
≥ 40ns*
CLK IN
t14
DB11
DB10
DB1
(MSB)
UNCERTAIN CONVERSION TIME FOR 30ns < t14 < 180ns
THE LTC1272 IS ALSO COMPATIBLE WITH THE AD7572 SYNCHRONIZATION MODES.
SEE “DIGITAL INTERFACE” TEXT.
Figure 13. RD and CLK IN for Synchronous Operation
t13
DB0
(LSB)
LTC1272 • TA15
Table 1. Data Bus Output, CS and RD = Low
PIN 4 PIN 5
PIN 6 PIN 7 PIN 8
Data Outputs* D11
D10
D9
D8
D7
HBEN = Low DB11 DB10
DB9
DB8
DB7
HBEN = High DB11 DB10
DB9
DB8
Low
Note: *D11 . . . D0/8 are the ADC data output pins
DB11 . . . DB0 are the 12-bit conversion results, DB11 is the MSB
PIN 9
D6
DB6
Low
PIN 10
D5
DB5
Low
PIN 11
D4
DB4
Low
PIN 13
D3/11
DB3
DB11
PIN 14
D2/10
DB2
DB10
PIN 15
D1/9
DB1
DB9
PIN 16
D0/8
DB0
DB8
12
Share Link: 
