LTC1272-3ACS View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1272-3ACS' PDF : 20 Pages View PDF
LTC1272
APPLICATI S I FOR ATIO
2.42V*
VREF
OUTPUT
ANALOG INPUT
(0V TO 5V) 10 Ω*
10µF
0.1µF
µP
DATA
BUS
LTC1272
A IN
VREF
AGND
VDD
NC¦
BUSY
D11 (MSB) CS
D10
RD
D9
HBEN
D8 CLK OUT
D7 CLK IN**
D6
D0/8
D5
D1/9
D4
D2/10
DGND D3/11
µP
CONTROL
LINES
0.1µF
–15V
10µ F
â€
0.1µF
5V
10µ F
* THE LTC1272 HAS THE SAME 0V TO 5V INPUT RANGE BUT PROVIDES A 2.42V
REFERENCE OUTPUT AS OPPOSED TO THE –5.25V OF THE AD7572. FOR PROPER
OPERATION, REVERSE THE REFERENCE CAPACITOR POLARITY AND SHORT OUT THE
10Ω RESISTOR.
** THE ADC CLOCK SHOULD BE SYNCHRONIZED TO THE CONVERSION START
SIGNALS (CS, RD) OR 1-2 LSBs OF OUTPUT CODE NOISE MAY OCCUR. DERIVING
THE ADC CLOCK FROM THE µP CLOCK IS ADEQUATE.
¦ THE LTC1272 CAN ACCOMMODATE THE –15V SUPPLY OF THE AD7572 BUT DOES
NOT REQUIRE IT. PIN 23 OF THE LTC1272 IS NOT INTERNALLY CONNECTED.
LTC1272 • TA04
Figure 22. Plugging the LTC1272 into an AD7572 Socket
Case 1: Clock Synchronous with CS and RD
If the clock signal for the AD7572 is derived from a
separate crystal or other signal which is not synchronous
with the microprocessor clock, then the signals need to be
synchronized for the LTC1272 to achieve best analog
performance (see Clock and Control Synchronization).
The best way to synchronize these signals is to drive the
CLK IN pin of the LTC1272 with a derivative of the
processor clock, as mentioned above and shown in Figure
22. Another way, shown in Figure 23, is to use a flip-flop
to synchronize the RD to the LTC1272 with the CLK IN
signal. This method will work but has two disavantages
over the first: because the RD is delayed by the flip-flop,
the actual conversion start and the enabling of the
LTC1272’s BUSY and data outputs can take up to one CLK
IN cycle to respond to a RD↓ convert command from the
processor. The sampling of the analog input no longer
occurs at the processor’s falling RD edge but may be
delayed as much as one CLK IN cycle. Although the
LTC1272 will still exhibit excellent DC performance, the
flip-flop will introduce jitter into the sampling which may
reduce the usefulness of this method for AC systems.
18
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