LTC1283CN View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1283CN' PDF : 24 Pages View PDF
LTC1283
APPLICATI S I FOR ATIO
differencing operation may not be performed accurately.
The conversion time is 44 ACLK cycles. Therefore, a
change in the “–” input voltage during this interval can
cause conversion errors. For a sinusoidal voltage on the
“–” input this error would be:
VERROR (MAX) = VPEAK × 2 × π × f(“–”) × 44/fACLK
Where f(“–”) is the frequency of the “–” input voltage,
VPEAK is its peak amplitude and fACLK is the frequency of
the ACLK. In most cases VERROR will not be significant. For
a 60Hz signal on the “–” input to generate a 1/4LSB error
(0.61mV) with the converter running at ACLK = 1MHz, its
peak value would have to be 38mV.
show examples of both adequate and poor settling.
Using a slower ACLK will allow more time for the refer-
ence to settle. However, even at the maximum ACLK rate
of 1MHz most references and op amps can be made to
settle within the 4µs bit time.
3. It is recommended that the REF – input be tied directly to
the analog ground plane. If REF– is biased at a voltage
other than ground, the voltage must not change during a
conversion cycle. This voltage must also be free of noise
and ripple with respect to analog ground.
5. Reference Inputs
The voltage between the reference inputs of the LTC1283
defines the voltage span of the A/D converter. The refer-
ence inputs look primarily like a 10k resistor but will have
transient capacitive switching currents due to the switched-
capacitor conversion technique (see Figure 14). During
each bit test of the conversion (every 4 ACLK cycles), a
capacitive current spike will be generated on the reference
pins by the A/D. These current spikes settle quickly and do
not cause a problem. However, if slow settling circuitry is
used to drive the reference inputs, care must be taken to
insure that transients caused by these current spikes settle
completely during each bit test of the conversion.
REF+
14
ROUT
10k
TYP
VREF REF–
13
LTC1283
EVERY 4 ACLK CYCLES
RON
5pF TO 30pF
HORIZONTAL: 1µs/DIV
Figure 15. Adequate Reference Settling
LTC1283 • F14
Figure 14. Reference Input Equivalent Circuit
When driving the reference inputs, three things should be
kept in mind:
1. The source resistance (ROUT) driving the reference
inputs should be low (less than 1Ω) to prevent DC drops
caused by the 300µA maximum reference current (IREF).
2. Transients on the reference inputs caused by the capaci-
tive switching currents must settle completely during
each bit test (each 4 ACLK cycles). Figures 15 and 16
HORIZONTAL: 1µs/DIV
Figure 16. Poor Reference Settling Can Cause A/D Errors
6. Reduced Reference Operation
The effective resolution to the LTC1283 can be increased by
reducing the input span of the converter. The LTC1283
exhibits good linearity and gain over a wide range of
reference voltages (see typical curves of Linearity and Gain
Error vs Reference Voltage). However, care must be taken
20
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