LTC1289CCSW View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1289CCSW' PDF : 28 Pages View PDF
LTC1289
APPLICATI S I FOR ATIO
The following discussion will demonstrate how the two
reference pins are to be used in conjunction with the
analog input multiplexer. In unipolar mode the input span
of the A/D is set by the difference in voltage on the REF+ pin
and the REF– pin. In the bipolar mode the input span is
twice the difference in voltage on the REF+ pin and the
REF– pin. In the unipolar mode the lower value of the input
span is set by the voltage on the COM pin for single-ended
inputs and by the voltage on the minus input pin for
differential inputs. For the bipolar mode of operation the
voltage on the COM pin or the minus input pin sets the
center of the input span.
The upper and lower value of the input span can now be
summarized in the following table:
INPUT
CONFIGURATION
UNIPOLAR MODE BIPOLAR MODE
Single-Ended Lower Value COM
–(REF+ – REF–) + COM
Upper Value (REF+ – REF–) + COM (REF+ – REF–) + COM
Differential
Lower Value IN–
–(REF+ – REF–) + IN–
Upper Value (REF+ – REF–) + IN– (REF+ – REF–) + IN–
The reference voltages REF+ and REF– can fall between
VCC and V –, but the difference (REF+– REF–) must be less
than or equal to
or equal to VCC
aVnCdC.gTrheeatienrptuhtavnolotar geeqsumal utostVb–e.less
than
The following examples are for a single-ended input con-
figuration.
Example 1: Let VCC = 3.3V, V– = 0V, REF+ = 3V, REF – = 1V
and COM = 0V. Unipolar mode of operation. The resulting
input span is 0V ≤ IN+ ≤ 2V.
Example 2: The same conditions as Example 1 except
COM = 1V. The resulting input span is 1V ≤ IN+ ≤ 3V. Note
if IN+ ≥ 3V the resulting DOUT word is all 1’s. If IN+ ≤ 1V then
the resulting DOUT word is all 0’s.
Example 3: Let VCC = 3.3V, V– = –3.3V, REF+ = 3V, REF–
= 1V and COM = 1V. Bipolar mode of operation. The
resulting input span is –1V ≤ IN+ ≤ 3V.
For differential input configurations with the same condi-
tions as in the above three examples the resulting input
spans are as follows:
Example 1 (Diff.): IN– ≤ IN+ ≤ IN– + 2V
Example 2 (Diff.): IN– ≤ IN+ ≤ IN– + 2V
Example 3 (Diff.): IN– – 2V ≤ IN+ ≤ IN– + 2V.
MSB-First/LSB-First Format (MSBF)
The output data of the LTC1289 is programmed for MSB-
first or LSB-first sequence using the MSBF bit. For MSB-
first output data, the input word clocked to the LTC1289
should always contain a logical one in the sixth bit location
(MSBF bit). Likewise for LSB-first output data the input
word clocked to the LTC1289 should always contain a zero
in the MSBF bit location. The MSBF bit affects only the
order of the output data word. The order of the input word
is unaffected by this bit.
MSBF
0
1
OUTPUT FORMAT
LSB-First
MSB-First
LTC1289 AI06
Word Length (WL1, WL0) and Power Shutdown
The last two bits of the input word (WL1 and WL0)
program the output data word length and the power
shutdown feature of the LTC1289. Word lengths of 8, 12
or 16 bits can be selected according to the following table.
WL1
WL0
0
0
0
1
1
0
1
1
OUTPUT WORD LENGTH
8 Bits
Power Shutdown
12 Bits
16 Bits
LTC1289 AI07
The WL1 and WL0 bits in a given DIN word control the
length of the present, not the next, DOUT word. WL1 and
WL0 are never “don’t cares” and must be set for the
correct DOUT word length even when a “dummy” DIN word
is sent. On any transfer cycle, the word length should be
made equal to the number of SCLK cycles sent by the
MPU. Power down will occur when WL1 = 0 and WL0 = 1
is selected. The previous result will be clocked out as a 10
bit word so a “dummy”conversion is required before
powering down the LTC1289. Conversions are resumed
once CS goes low or an SCLK is applied, if CS is already
low.
12
Share Link: 
