LTC1289CCSW View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1289CCSW' PDF : 28 Pages View PDF
LTC1289
APPLICATI S I FOR ATIO
Deglitcher
A deglitching circuit has been added to the Chip Select
input of the LTC1289 to minimize the effects of errors
caused by noise on that input. This circuit ignores changes
in state on the CS input that are shorter in duration than
one ACLK cycle. After a change of state on the CS input, the
LTC1289 waits for two falling edge of the ACLK before
recognizing a valid chip select. One indication of CS
recognition is the DOUT line becoming active (leaving the
Hi-Z state). Note that the deglitching applies to both the
rising and falling CS edges.
Low CS Recognized Internally
CS Low During Conversion
In the normal mode of operation, CS is brought high
during the conversion time. The serial port ignores any
SCLK activity while CS is high. The LTC1289 will also
operate with CS low during the conversion. In this mode,
SCLK must remain low during the conversion as shown in
the following figure. After the conversion is complete, the
DOUT line will become active with the first output bit. Then
the data transfer can begin as normal.
High CS Recognized Internally
ACLK
ACLK
CS
Hi-Z
DOUT
VALID OUTPUT
LTC1289 AI08
CS
DOUT
VALID OUTPUT
Hi-Z
LTC1289 AI08a
CS
SCLK
DIN
DOUT
SHIFT
MUX ADDRESS
IN
tSMPL
SAMPLE ANALOG
INPUT
48 TO 52
ACLK CYC
SHIFT RESULT OUT
AND NEW ADDRESS IN
DON'T CARE
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Figure 3. CS High During Conversion
LTC1289 AIF03
CS
SCLK
DIN
DOUT
14
SHIFT
MUX ADDRESS
IN
tSMPL
SAMPLE ANALOG
INPUT
48 TO 52
ACLK CYC
SCLK MUST
REMAIN LOW
SHIFT RESULT OUT
AND NEW ADDRESS IN
DON'T CARE
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Figure 4. CS Low During Conversion
LTC1289 AIF04
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