UU U
PI FU CTIO S
CONVST (Pin 23): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
CS (Pin 24): Chip Select. The input must be low for the
ADC to recognize CONVST and RD inputs.
BUSY (Pin 25): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data
valid on the rising edge of BUSY.
LTC1409
VSS (Pin 26): – 5V Negative Supply. Bypass to AGND
using 10µF tantalum in parallel 0.1µF or 10µF ceramic.
OVDD (Pin 27): Positive Supply for Output Drivers. For
5V logic, short to Pin 28. For 3V logic, short to supply
of the logic being driven.
AVDD (Pin 28): 5V Positive Supply. Bypass to AGND
10µF tantalum in parallel with 0.1µF or 10µF ceramic.
UU
W
FU CTIO AL BLOCK DIAGRA
+AIN
– AIN
VREF
REFCOMP
(4.06V)
AGND
DGND
4k
2.5V REF
REF AMP
INTERNAL
CLOCK
CSAMPLE
CSAMPLE
ZEROING SWITCHES
AVDD
12-BIT CAPACITIVE DAC
SUCCESSIVE APPROXIMATION
REGISTER
CONTROL LOGIC
+
COMP
–
12
OUTPUT LATCHES
OVDD
•••
D11
D0
OGND
NAP/SLP SHDN RD CONVST CS BUSY
LTC1409 • BD
TEST CIRCUITS
Load Circuits for Access Timing
5V
DBN
1k
1k
DBN
CL
CL
(a) Hi-Z to VOH
and VOL to VOH
LTC1409 • TC01
(b) Hi-Z to VOL
and VOH to VOL
Load Circuits for Bus Relinquish Time
5V
DBN
1k
100pF
(a) VOH to Hi-Z
1k
DBN
100pF
LTC1409 • TC02
(b) VOL to Hi-Z
7