LTC1421 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1421' PDF : 24 Pages View PDF
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
Board Removal Timing
When the board is removed from the host, the sequence
happens in reverse (Figure 17). Since CON1 and CON2 are
the shortest pins, they break connection first and are
internally pulled high (time point 1). The charge pumps are
turned off, CPON is pulled low. VOUTLO and VOUTHI are
actively pulled down. When VOUTLO falls below its reset
threshold (time point 2) PWRGD is pulled low. To allow
time for power fail information to be stored in nonvolatile
memory, the falling edge of RESET (time point 3) is
delayed by 32µs from the falling edged of PWRGD.
Finally, the input supply pins VCCHI and VCCLO break
contact (time point 4). If staggered pins are not used, the
board may be powered down prior to removal by switch-
ing the POR pin to ground with a toggle switch.
1
VCCLO
VCCHI
DISABLE
CON1
CON2
CPON
GATEHI
2
3
4
32µs
VOUTHI
GATELO
VOUTLO
PWRGD
RESET
FAULT
POR
VTH2
1421 F17
Figure 17. Board Removal Timing
16
Share Link: 
