LTC1426IS8 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1426IS8' PDF : 8 Pages View PDF
LTC1426
APPLICATIONS INFORMATION
where VPWM is the no load DAC output voltage, RL is the
resistive load and ROUT is the DAC output impedance.
Therefore, the resistive load RL should be sufficiently large
to ignore the effect of output impedance on the load
voltage.
Figure 2 shows a typical lowpass filter recommended to
filter the PWM outputs. Without filtering, results obtained
from unfiltered outputs can be erroneous when taking
measurements from a voltmeter. The ratio of the filter time
constant, t, to the PWM frequency determines the amount
of output ripple frequency that feeds into the system. In
addition, the loading of the output also determines an
additional error voltage drop across R1.
R1
10k
INPUT
C1
0.1µF
OUTPUT
1426 F02
Figure 2. Lowpass Filter for PWM Averaging
Digital Interface
The LTC1426 can be controlled by using one of two
interface modes: pulse mode and pushbutton mode. The
operating interface mode is determined during power-
up. If both CLK1 and CLK2 inputs are floating on power-up,
then an interface mode detect circuit configures the chip
in pushbutton mode until the next VCC reset (Figure 3).
However, if either of CLK1 or CLK2 is at logic 0 or 1 at
power-up, then the chip configures in pulse mode until
the next VCC reset.
Figure 3 shows the simplified logic for determining the
interface mode at power-up. A set of pull-up/pull-down
resistors allow the LTC1426 to sense the state of the CLK
pins at power-up. If both CLK1 and CLK2 pins are floating
on power-up then the control signal from the LTC1426
leaves these resistors in place, allowing the LTC1426 to
detect three operating states at each CLK pin: high, low
and “middle” (floating). If the CLK pins are tied to either
logic 0 or 1 at power-up, then the control signal will
disconnect these resistors, making CLK1 and CLK2 CMOS
compatible input pins.
Note that both CLK pins will always be in the same mode.
If one pin is floating and the other is at logic high/low on
power-up, the LTC1426 will assume pulse mode.
CLK1
CLK2
VCC
INTERNAL LOGIC
CLK1 INPUT
CLK2 INPUT
CONTROL
LTC1426
1426 F03
Figure 3. Interface Mode Detect Circuit
TYPICAL APPLICATIONS N
Typical applications for this part include digital calibration,
industrial process control, automatic test equipment, cel-
lular telephones and portable battery-powered applications.
Figures 4 and 5 show how easy this part is to use. In all
applications, the PWM full-scale output voltage is set by
VREF. This makes interfacing convenient when a variety of
reference spans are needed.
Pulse Mode
Figure 4 shows the LTC1426 in a pulse mode, stand-alone
application. The LTC1426 can interface directly with
minimum external components to most popular micro-
processors (MPUs). The Intel 8051 was chosen to dem-
onstrate direct interface for the LTC1426, as this
MPU
(e.g. 8051)
P1.0
P1.1
VCC
2.7V TO 5.5V
1
2
3
4
PWM1
LTC1426
CLK1 SHDN
CLK2 VCC
GND VREF
PWM1 PWM2
8
SHDN
7
6 VREF
0V TO 5.5V
5
PWM2
0.1µF
PWM1/PWM2: 0V TO 0.985(VREF)
1426 F04
Figure 4. Stand-Alone Pulse Mode Interface
6
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