LTC1426IS8 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1426IS8' PDF : 8 Pages View PDF
LTC1426
TYPICAL APPLICATIONS N
microprocessor has “quasi-bidirectional” ports that elimi-
nate additional pull-up resistors to VCC. However, external
pull-up resistors should be used if the microprocessor
doesn’t pull the port pins high during reset.
In pulse mode, each clock pulse applied to the CLK1 or
CLK2 input increments the respective counter by one
count. When the counter increases beyond full scale
(111111B), the counter rolls over and becomes zero scale
(000000B). In this way, a single pulse applied to the CLK1
or CLK2 input increases the respective counter by one
count, and 63 pulses decrease that counter by one count.
Pushbutton Mode
Figure 5 shows how to use the LTC1426 in a typical
pushbutton application. In pushbutton mode, a logic 1
pulse applied to the CLK1 or CLK2 input increments the
VCC
2.7V TO 5.5V
R
R
UP
UP
DOWN DOWN
VCC
2.7V TO 5.5V
1
2
3
4
PWM1
LTC1426
CLK1 SHDN
CLK2 VCC
GND VREF
PWM1 PWM2
8
SHDN
7
6 VREF
0V TO 5.5V
5
PWM2
0.1µF
PWM1/PWM2: 0V TO 0.985(VREF)
1426 F05
LIMITING RESISTOR R PREVENTS SHORTING OF VCC AND GND WHEN BOTH
BUTTONS ARE SIMULTANEOUSLY PUSHED. THIS RESISTOR CAN BE PLACED
EITHER IN THE VCC OR GND LEG AND THIS DETERMINES THE FUNCTION WHEN
BOTH BUTTONS ARE PUSHED. VALUE OF R < 50k
Figure 5. Pushbutton Mode Interface
respective counter by one count, and stops incrementing
when the counter reaches full scale (111111B). A logic 0
pulse applied to the CLK1 or CLK2 input decrements the
respective counter by one count, and stops decrementing
when the counter reaches zero scale (000000B). An on-
chip debouncing circuit has a debounce time of 12.8ms to
prevent unintended counts with bouncing pushbuttons.
After a time delay of 410ms, the counter will begin to
increment/decrement at a repeat rate of 19.5Hz if the
pushbutton remains pressed.
Care should be taken to avoid running the CLK and PWM
traces close to one another. Since the CLK pins are high
impedance input nodes in pushbutton mode, current
spikes caused by the switching of the PWM outputs
feedthrough via any stray capacitance between PWM and
CLK lines if not properly routed. Use of proper grounding
techniques and spacing of these lines are highly recom-
mended for optimal performance.
Figure 6 shows a dual digitally programmable current
source using the LT®1013 dual precision op amp and two
NPN transistors (2N3904). After the lowpass filter combi-
nation of R1, C1 (R2, C2), its output swings from 0V to
4.93V. In the configuration shown, this voltage will be
forced across the resistor RA1 (RA2). If RA1 (RA2) is chosen
to be 493Ω, the output current will range from 0mA at zero
scale to 10mA at full scale. The minimum voltage for VS is
determined by the load resistor RL1 (RL2) and Q1(Q2)’s
VCESAT voltage. With a load resistor of 50Ω, the voltage
source can be as low as 5V.
MPU
(e.g. 8051)
P1.0
P1.1
SHDN
5V
VS
LTC1426
1
8
CLK1 SHDN
2
7
CLK2 VCC
3
6
GND VREF
4
5
PWM1 PWM2
RL1
0.1µF
2N3904
R1
10k
R2
10k
RA1
493Ω
C1
0.1µF
C2
0.1µF
10V
VS
RL2
0.1µF
LT1013
1
OUT A
V+ 8
2
7
–IN A OUT B
3
+IN A
4 V–
6
– IN B
5
+ IN B
1426 F06
2N3904
RA2
493Ω
IOUT1/IOUT2: 0mA TO 10mA
RL1/RL2: < 50Ω
VS: 5V TO 30V
Figure 6. Dual Digitally Programmable Current Source
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
7
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