LTC1553L
APPLICATIONS INFORMATION
ground plane at a single point, preferably at a fairly quiet
point in the circuit such as close to the output capaci-
tors. This is not always practical, however, due to
physical constraints. Another reasonably good point to
make this connection is between the output capacitors
and the source connection of the low side FET Q2. Do
not tie this single point ground in the trace run between
the low side FET source and the input capacitor ground,
as this area of the ground plane will be very noisy.
3. The small signal resistors and capacitors for frequency
compensation and soft start should be located very
close to their respective pins and the ground ends
connected to the signal ground pin through a separate
trace. Do not connect these parts to the ground plane!
4. The VCC and PVCC decoupling capacitors should be as
close to the LTC1553L as possible. The 10µF bypass
capacitors shown at VCC and PVCC will help provide
optimum regulation performance.
5. The (+) plate of CIN should be connected as close as
possible to the drain of the upper MOSFET. An addi-
tional 1µF ceramic capacitor between VIN and power
ground is recommended.
6. The SENSE pin is very sensitive to pickup from the
switching node. Care should be taken to isolate SENSE
from possible capacitive coupling to the inductor switch-
ing signal. A 0.1µF is required between the SENSE pin
and the SGND pin next to the LTC1553L.
7. OUTEN is a high impedance input and should be
externally pulled up to a logic HIGH for normal
operation.
8. Kelvin sense IMAX and IFB at Q1 drain and source pins.
VIN
VOUT
+
CIN
Q1
LO
+
COUT
Q2
BOLD LINES INDICATE
HIGH CURRENT PATHS
1 G2 LTC1553L G1 20
PVCC
+
10µF
+
10µF
2
0.1µF 3
PVCC
GND
4 SGND
0.1µF
5 VCC
19
OUTEN
18
VID0
VID0
17
VID1
VID1
16
VID2
VID2
15
VID3
VID3
RIMAX
RIFB
6 SENSE
7
IMAX
8
IFB
9
SS
14
VID4
VID4
13
PWRGD
12
FAULT
10
COMP
CSS
C1 RC
0.1µF
11
OT
CC
5.6k
5.6k
5.6k
1153L F10
Figure 10. LTC1553L Layout Diagram
18