LTC1864LCMS8 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC1864LCMS8' PDF : 16 Pages View PDF
LTC1864L/LTC1865L
APPLICATIO S I FOR ATIO
LTC1864L OPERATION
Operating Sequence
The LTC1864L conversion cycle begins with the rising
edge of CONV. After a period equal to tCONV, the conver-
sion is finished. If CONV is left high after this time, the
LTC1864L goes into sleep mode drawing only leakage
current. On the falling edge of CONV, the LTC1864L goes
into sample mode and SDO is enabled. SCK synchronizes
the data transfer with each bit being transmitted from SDO
on the falling SCK edge. The receiving system should
capture the data from SDO on the rising edge of SCK. After
completing the data transfer, if further SCK clocks are
applied with CONV low, SDO will output zeros indefinitely.
See Figure 1.
Analog Inputs
The LTC1864L has a unipolar differential analog input. The
converter will measure the voltage between the “IN+” and
“IN–” inputs. A zero code will occur when IN+ minus IN–
equals zero. Full scale occurs when IN+ minus IN– equals
VREF minus 1LSB. See Figure 2. Both the “IN+” and
“IN–” inputs are sampled at the same time, so common
mode noise on the inputs is rejected by the ADC. If “IN–”
is grounded and VREF is tied to VCC, a rail-to-rail input span
will result on “IN+” as shown in Figure 3.
Reference Input
The voltage on the reference input of the LTC1864L
defines the full-scale range of the A/D converter. The
LTC1864L can operate with reference voltages from VCC to
1V.
CONV
SCK
tCONV
DON'T CARE
SLEEP MODE
tSMPL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SDO
Hi-Z
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
Hi-Z
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
1854 F01
Figure 1. LTC1864L Operating Sequence
1111111111111111
1111111111111110
•
•
•
0000000000000001
0000000000000000
*VIN = IN+ – IN–
Figure 2. LTC1864L Transfer Curve
1µF
VCC
LTC1864L
1
VREF
VIN = 0V TO VCC 2 IN+
VIN*
3 IN–
8
VCC
7
SCK
6
SDO
4
5
GND CONV
1864 F03
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
1864 F02
Figure 3. LTC1864L with Rail-to-Rail Input Span
sn18645L 18645Lfs
9
Share Link: 
