LTC2190 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC2190' PDF : 28 Pages View PDF
LTC2192
LTC2191/LTC2190
APPLICATIONS INFORMATION
DIGITAL OUTPUTS
The digital outputs of the LTC2192/LTC2191/LTC2190 are
serialized LVDS signals. Each channel outputs one bit at
a time (1-lane mode), two bits at a time (2-lane mode) or
four bits at a time (4-lane mode). Please refer to the Tim-
ing Diagrams for details. In 4-lane mode the clock duty
cycle stabilizer must be enabled.
The output data should be latched on the rising and falling
edges of the data clock out (DCO). A data frame output
(FR) can be used to determine when the data from a new
conversion result begins.
The maximum serial data rate for the data outputs is 1Gbps,
so the maximum sample rate of the ADC will depend on
the serialization mode as well as the speed grade of the
ADC (See Table 1). The minimum sample rate for all se-
rialization modes is 5Msps.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground.
Table 1. Maximum Sampling Frequency for All Serialization
Modes. Note That These Limits are for the LTC2192. The
Sampling Frequency for the Slower Speed Grades Cannot
Exceed 40MHz (LTC2191) or 25MHz (LTC2190)
MAXIMUM
SAMPLING
SERIALIZATION FREQUENCY, DCO
FR
SERIAL
MODE
fS (MHz) FREQUENCY FREQUENCY DATA RATE
4-Lane
65
2 • fS
fS
4 • fS
2-Lane
65
4 • fS
fS
8 • fS
1-Lane
62.5
8 • fS
fS
16 • fS
Programmable LVDS Output Current
In LVDS mode, the default output driver current is 3.5mA.
This current can be adjusted by control register A2 in the
serial programming mode. Available current levels are
1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
In the parallel programming mode the SDO pin can select
either 3.5mA or 1.75mA.
Optional LVDS Driver Internal Termination
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A2. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When
the internal termination is enabled, the output driver
current is doubled to maintain the same output voltage
swing. Internal termination can only be selected in serial
programming mode.
DATA FORMAT
Table 2 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A1.
Table 2. Output Codes vs Input Voltage
AIN+-AIN–
(2V RANGE)
D15-D0
(OFFSET BINARY)
>1.000000V
+0.999970V
+0.999939V
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1110
+0.000030V
+0.000000V
–0.000030V
–0.000061V
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0111 1111 1111 1110
–0.999939V
–1.000000V
<–1.000000V
0000 0000 0000 0001
0000 0000 0000 0000
0000 0000 0000 0000
D15-D0
(2’ s COMPLEMENT)
0111 1111 1111 1111
0111 1111 1111 1111
0111 1111 1111 1110
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
1000 0000 0000 0001
1000 0000 0000 0000
1000 0000 0000 0000
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off-chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
219210p
21
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