LTC2190 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC2190' PDF : 28 Pages View PDF
LTC2192
LTC2191/LTC2190
APPLICATIONS INFORMATION
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be writ-
ten to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the Timing
Diagrams). During a read back command the register is
not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and read back is not needed,
then SDO can be left floating and no pull-up resistor is
needed.
Table 4 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
should be programmed as soon as possible after the power
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset is
complete, bit D7 is automatically set back to zero.
Table 4. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
D5
D4
D3
D2
D1
D0
RESET
X
X
X
X
X
X
X
Bit 7
RESET
Software Reset Bit
0 = Not Used
1 = Software Reset. All Mode Control Registers are Reset to 00h. The ADC is Momentarily Placed in Sleep Mode.
This Bit is Automatically Set Back to Zero After the Reset is Complete
Bits 6-0
Unused, Don’t Care Bits.
REGISTER A1: FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h)
D7
D6
D5
D4
D3
D2
DCSOFF
RAND
TWOSCOMP
SLEEP
NAP_2
X
Bit 7
DCSOFF
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer On
1 = Clock Duty Cycle Stabilizer Off. This is not recommended.
Bit 6
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
Bit 5
TWOSCOMP
Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
Bits 4, 3, 0
SLEEP:NAP_2:NAP_1 Sleep/Nap Mode Control Bits
000 = Normal Operation
0X1 = Channel 1 in Nap Mode
01X = Channel 2 in Nap Mode
1XX = Sleep Mode. Both Channels are Disabled.
Note: Any Combination of Channels Can Be Placed in Nap Mode
Bits 1, 2
Unused, Don’t Care Bits
D1
D0
X
NAP_1
219210p
23
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