LTC2205/LTC2204
APPLICATIONS INFORMATION
DIGITAL OUTPUTS
Digital Output Buffers
Figure 11 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated
from the ADC power and ground. The additional N-channel
transistor in the output driver allows operation down to
low voltages. The internal resistor in series with the output
eliminates the need for external damping resistors.
As with all high speed/high resolution converters, the digital
output loading can affect the performance. The digital
outputs of the LTC2205/LTC2204 should drive a minimum
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as a ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF. A resistor in series with the
output may be used but is not required since the ADC has
a series resistor of 33Ω on chip.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Data Format
The LTC2205/LTC2204 parallel digital output can be
selected for offset binary or 2’s complement format. The
format is selected with the MODE pin. This pin has a four
level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD.
An external resistor divider can be user to set the 1/3VDD
and 2/3VDD logic levels. Table 1 shows the logic states
for the MODE pin.
Table 1. MODE Pin Function
MODE
0(GND)
1/3VDD
2/3VDD
VDD
Output Format
Offset Binary
Offset Binary
2’s Complement
2’s Complement
Clock Duty
Cycle Stabilizer
Off
On
On
Off
Overflow Bit
An overflow output bit (OF) indicates when the converter
is over-ranged or under-ranged. A logic high on the OF
pin indicates an overflow or underflow.
VDD
DATA
FROM
LATCH
PREDRIVER
LOGIC
LTC2205/LTC2204
OVDD 0.5V
VDD
TO 3.6V
0.1μF
OVDD
33Ω
TYPICAL
DATA
OUTPUT
OGND
22054 F11
Figure 11. Equivalent Circuit for a Digital Output Buffer
22054fc
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