TIMING DIAGRAMS
Full-Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
LTC2259-16
ANALOG
INPUT
ENC–
ENC+
D0-D15
CLKOUT+
CLKOUT –
tAP
N
tH
N+1
tL
N+2
N+3
N+4
tD
N–5
tC
N–4
N–3
N–2
N–1
225916 TD01
ANALOG
INPUT
ENC–
ENC+
D0_1
•••
D14_15
CLKOUT+
CLKOUT –
Double-Data Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
tAP
N
tH
N+1
tL
N+2
N+3
N+4
tD
D0N-5
D1N-5 D0N-4
tD
D1N-4
D0N-3 D1N-3
D0N-2
D1N-2
D14N-5 D15N-5 D14N-4 D15N-4 D14N-3 D15N-3 D14N-2 D15N-2
tC
tC
225916 TD02
225916f
7