LTC2941CDCB-TRPBF View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC2941CDCB-TRPBF' PDF : 16 Pages View PDF
LTC2941
APPLICATIONS INFORMATION
SDA
a6 - a0
b7 - b0
b7 - b0
SCL
S
START
CONDITION
1-7
ADDRESS
8
9
R/W
ACK
1-7
8
9
DATA
ACK
1-7
8
DATA
Figure 4. Data Transfer Over I2C or SMBus
9
P
ACK
STOP
CONDITION
2941 F04
Start and Stop Conditions
When the bus is idle, both SCL and SDA must be high. A
bus master signals the beginning of a transmission with
a START condition by transitioning SDA from high to low
while SCL is high. When the master has finished com-
municating with the slave, it issues a STOP condition by
transitioning SDA from low to high while SCL is high. The
bus is then free for another transmission. When the bus is
in use, it stays busy if a repeated START (Sr) is generated
instead of a STOP condition. The repeated START (Sr)
conditions are functionally identical to the START (S).
Data Transmission
After a START condition, the I2C bus is considered busy
and data transfer begins between a master and a slave. As
data is transferred over I2C in groups of nine bits (eight
data bits followed by an acknowledge bit), each group
takes nine SCL cycles. The transmitter releases the SDA
line during the acknowledge clock pulse and the receiver
issues an acknowledge (ACK) by pulling SDA low or leaves
SDA high to indicate a not-acknowledge (NAK) condition.
Change of data state can only happen while SCL is low.
Write Protocol
The master begins communication with a START condi-
tion followed by the seven bit slave address 1100100
and the R/W bit set to zero, as shown in Figure 5. The
LTC2941 acknowledges this by pulling SDA low and then
the master sends a command byte which indicates which
internal register the master is to write. The LTC2941
acknowledges and then latches the command byte into
its internal register address pointer. The master delivers
the data byte, the LTC2941 acknowledges once more and
latches the data into the desired register. The transmission
is ended when the master sends a STOP condition. If the
master continues by sending a second data byte instead
of a stop, the LTC2941 acknowledges again, increments
its address pointer and latches the second data byte in
the following register, as shown in Figure 6.
Read Protocol
The master begins a read operation with a START condition
followed by the seven bit slave address 1100100 and the
R/W bit set to zero, as shown in Figure 7. The LTC2941
acknowledges and then the master sends a command
byte which indicates which internal register the master is
to read. The LTC2941 acknowledges and then latches the
command byte into its internal register address pointer. The
master then sends a repeated START condition followed
by the same seven bit address with the R/W bit now set
to one. The LTC2941 acknowledges and sends the con-
tents of the requested register. The transmission is ended
when the master sends a STOP condition. If the master
acknowledges the transmitted data byte, the LTC2941
increments its address pointer and sends the contents of
the following register as shown in Figure 8.
2941f
12
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