LTC2942I View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC2942I' PDF : 16 Pages View PDF
LTC2942
APPLICATIONS INFORMATION
Data Transmission
After a START condition, the I2C bus is considered busy
and data transfer begins between a master and a slave. As
data is transferred over I2C in groups of nine bits (eight
data bits followed by an acknowledge bit), each group
takes nine SCL cycles. The transmitter releases the SDA
line during the acknowledge clock pulse and the receiver
issues an acknowledge (ACK) by pulling SDA low or leaves
SDA high to indicate a not acknowledge (NAK) condition.
Change of data state can only happen while SCL is low.
Write Protocol
The master begins a write operation with a START condi-
tion followed by the seven bit slave address 1100100
and the R/W bit set to zero, as shown in Figure 4. The
LTC2942 acknowledges this by pulling SDA low and then
the master sends a command byte which indicates which
internal register the master is to write. The LTC2942 ac-
knowledges and latches the command byte into its internal
register address pointer. The master delivers the data byte,
the LTC2942 acknowledges once more and latches the
data into the desired register. The transmission is ended
when the master sends a STOP condition. If the master
continues by sending a second data byte instead of a stop,
the LTC2942 acknowledges again, increments its address
pointer and latches the second data byte in the following
register, as shown in Figure 5.
Read Protocol
The master begins a read operation with a START condition
followed by the seven bit slave address 1100100 and the
R/W bit set to zero, as shown in Figure 6. The LTC2942
SDA
a6 - a0
b7 - b0
b7 - b0
SCL
S
START
CONDITION
1-7
ADDRESS
8
9
1-7
8
9
1-7
8
R/W
ACK
DATA
ACK
DATA
Figure 3. Data Transfer Over I2C or SMBus
9
P
ACK
STOP
CONDITION
2942 F03
S ADDRESS W A REGISTER A DATA A P
1100100 0 0 01h 0 FCh 0
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
2942 F04
A: ACKNOWLEDGE (LOW)
A: NOT ACKNOWLEDGE (HIGH)
S: START CONDITION
P: STOP CONDITION
R: READ BIT (HIGH)
W: WRITE BIT (LOW)
Figure 4. Writing FCh to the LTC2942 Control Register (B)
S ADDRESS W A REGISTER A DATA A DATA A P
1100100 0 0
02h
0 F0h 0 01h 0
2942 F05
Figure 5. Writing F001h to the LTC2942
Accumulated Charge Register (C, D)
S ADDRESS W A REGISTER A S ADDRESS R A DATA A P
1100100 0 0 00h 0
1100100 1 0 01h 1
2942 F06
Figure 6. Reading the LTC2942 Status Register (A)
S ADDRESS W A REGISTER A S ADDRESS R A DATA A DATA A P
1100100 0 0 08h 0
1100100 1 0 F1h 0 24h 1
2942 F07
Figure 7. Reading the LTC2942 Voltage Register (I, J)
2942f
13
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